Analog-to-digital converter, measurement arrangement and method for analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-10826523-B2
Application number	US-201816611118-A
Country	US
Kind code	B2
Filing date	May 4, 2018
Priority date	May 9, 2017
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

An analog-to-digital converter ( 10 ) comprises a first and a second sampling capacitor ( 24, 25 ), a first integrator ( 26 ), a first and a second input switch ( 31, 32 ) coupling a first input terminal ( 11 ) and a common mode terminal ( 39 ) to a first electrode of the first sampling capacitor ( 24 ), a third and a fourth input switch ( 33, 34 ) coupling a second input terminal ( 12 ) and the common mode terminal ( 39 ) to a first electrode of the second sampling capacitor ( 25 ), a fifth and a sixth input switch ( 35, 36 ) coupling a second electrode of the first sampling capacitor ( 24 ) to an amplifier common mode terminal ( 40 ) and the first integrator input ( 27 ), and a seventh and an eighth input switch ( 37, 38 ) coupling a second electrode of the second sampling capacitor ( 25 ) to the amplifier common mode terminal ( 40 ) and the second integrator input ( 28 ).

First claim

The invention claimed is:

1. An analog-to-digital converter, comprising
a first and a second sampling capacitor,
a first integrator having a first and a second integrator input,
a first and a second input switch that couple a first input terminal and a common mode terminal to a first electrode of the first sampling capacitor,
a third and a fourth input switch that couple a second input terminal and the common mode terminal to a first electrode of the second sampling capacitor,
a fifth and a sixth input switch that couple a second electrode of the first sampling capacitor to an amplifier common mode terminal and to the first integrator input, and
a seventh and an eighth input switch that couple a second electrode of the second sampling capacitor to the amplifier common mode terminal and to the second integrator input.

2. The analog-to-digital converter according to claim 1 ,
wherein the first integrator comprises
an amplifier having a first amplifier input connected to the first integrator input and a second amplifier input connected to the second integrator input,
a first integrating capacitor coupled to the first amplifier input and to a first amplifier output of the amplifier, and
a second integrating capacitor coupled to the second amplifier input and to a second amplifier output of the amplifier.

3. The analog-to-digital converter according to claim 2 ,
wherein the amplifier is connected to the amplifier common mode terminal.

4. The analog-to-digital converter according to claim 2 ,
wherein the analog-to-digital converter comprises
a second integrator coupled on its input side to the first and the second amplifier output,
a comparator coupled on its input side to an output side of the second integrator and
a filter coupled on its input side to the output side of the second integrator.

5. The analog-to-digital converter according to claim 1 ,
wherein the analog-to-digital converter is configured as a sigma-delta modulator.

6. The analog-to-digital converter according to claim 1 ,
wherein the analog-to-digital converter comprises
a first clock generator having a first output connected to the fifth and the seventh input switch and a second output connected to the sixth and eighth input switch and
a second clock generator having a first output connected to at least one of the first and the third input switch and a second output connected to at least one of the second and the fourth input switch.

7. The analog-to-digital converter according to claim 6 ,
wherein the first and the second clock generator are coupled such that the first, third, fifth and seventh input switch receive a first logical signal and the second, fourth, sixth and eighth input switch receive a second logical signal.

8. The analog-to-digital converter according to claim 6 ,
wherein the first to the fourth input switch, the first and the second sampling capacitor and the second clock generator are configured to operate at a higher voltage level than the fifth to the eighth input switch and the first clock generator.

9. The analog-to-digital converter according to claim 6 ,
wherein the second clock generator comprises
an input stage connected on its input side to a first input of the second clock generator,
an intermediate stage and
an output stage connected on its output side to the first output of the second clock generator,
wherein the intermediate stage couples the input stage to the output stage.

10. The analog-to-digital converter according to claim 1 ,
wherein the analog-to-digital converter comprises a resistive voltage divider having a first resistor coupling the first input terminal to the common mode terminal and a second resistor coupling the common mode terminal to the second input terminal.

11. A measurement arrangement, comprising
an analog-to-digital converter,
a first cell and
a coupler coupling a first terminal of the first cell to a first input terminal and a second terminal of the first cell to a second input terminal,
wherein the analog-to-digital converter comprises
a first and a second sampling capacitor,
a first integrator having a first and a second integrator input,
a first and a second input switch that couple the first input terminal and a common mode terminal to a first electrode of the first sampling capacitor,
a third and fourth input switch that couple the second input terminal and the common mode terminal to a first electrode of the second sampling capacitor,
a fifth and a sixth input switch that couple a second electrode of the first sampling capacitor to an amplifier common mode terminal and to the first integrator input, and
a seventh and an eighth input switch that couple a second electrode of the second sampling capacitor to the amplifier common mode terminal and to the second integrator input.

12. The measurement arrangement according to claim 11 ,
wherein the measurement arrangement comprises at least a second cell and the coupler selectively couples
the first terminal of the first cell to the first input terminal and the second terminal of the first cell to the second input terminal or
a first terminal of the second cell to the first input terminal and a second terminal of the second cell to the second input terminal.

13. A measurement arrangement,
comprising an analog-to-digital converter and a resistive sensor having a first terminal connected to a first input terminal and a second terminal connected to a second input terminal,
wherein the analog-to-digital converter comprises
a first and a second sampling capacitor,
a first integrator having a first and a second integrator input,
a first and a second input switch that couple the first input terminal and a common mode terminal to a first electrode of the first sampling capacitor,
a third and a fourth input switch that couple the second input terminal and the common mode terminal to a first electrode of the second sampling capacitor,
a fifth and a sixth input switch that couple a second electrode of the first sampling capacitor to an amplifier common mode terminal and to the first integrator input, and
a seventh and an eighth input switch that couple a second electrode of the second sampling capacitor to the amplifier common mode terminal and to the second integrator input.

14. The measurement arrangement according to claim 13 ,
wherein the resistive sensor comprises a first and a second resistive element and a tap, and
wherein the first resistive element couples the first terminal of the resistive sensor to the tap of the resistive sensor, the second resistive element couples the tap of the resistive sensor to the second terminal of the resistive sensor and the tap of the resistive sensor is connected to the common mode terminal.

15. A method for analog-to-digital conversion, comprising
in a first phase, sampling a first difference between a first input voltage and an amplifier common mode voltage by a first sampling capacitor and sampling a second difference between a second input voltage and the amplifier common mode voltage by a second sampling capacitor, and
in a second phase, providing a first integrator voltage to a first integrator input of a first integrator by subtracting the first difference voltage from a input common mode voltage and providing a second integrator voltage to a second integrator input of the first integrator by subtracting the second difference voltage from the input common mode voltage, and
generating a digital output signal by digitizing an integrator difference voltage between the first integrator voltage and the second integrator voltage.

Assignees

• Ams Ag

Inventors

• Adusumalli Ravi Kumar
• Singamala Sudhakar
• Vulligaddala Veeresh Babu
• Ranganathan Rohit
• Nyshadham Chandra
• Avalur Krishna Kanth
• Sasikala Jayachandran Pillai Parvathy

Classifications

• G01R31/382

  Arrangements for monitoring battery or accumulator variables, e.g. SoC · CPC title

• H03M1/1295

  Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• Y02T10/70

  Energy storage systems for electromobility, e.g. batteries · CPC title