Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12417908-B2
Application number	US-202217839048-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Oct 13, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

According to the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first metal layer provided above the semiconductor substrate;
a second metal layer provided above the first metal layer and containing Ni as a material; and
a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein
the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer,
the third metal layer is harder than the first metal layer, and
the second metal layer directly contacts the first metal layer.

2. The semiconductor device according to claim 1 , wherein the second metal layer contains P as an impurity.

3. The semiconductor device according to claim 1 , further comprising a barrier metal layer provided between the semiconductor substrate and the first metal layer,
wherein the barrier metal layer is harder than the first metal layer.

4. The semiconductor device according to claim 1 , further comprising an insulating film provided between the semiconductor substrate and the first metal layer and having an opening formed to expose the semiconductor substrate,
wherein the first metal layer is electrically connected to the semiconductor substrate through the opening.

5. The semiconductor device according to claim 4 , further comprising a fourth metal layer that is provided in the opening and electrically connects the semiconductor substrate and the first metal layer.

6. The semiconductor device according to claim 4 , wherein a plurality of the openings are formed in the insulating film in a dot shape in a plan view.

7. The semiconductor device according to claim 6 , wherein unevenness is formed on an upper surface of the third metal layer.

8. The semiconductor device according to claim 1 , further comprising an adhesion layer that brings the second metal layer and the third metal layer into close contact with each other.

9. The semiconductor device according to claim 1 , further comprising an Au layer provided between the second metal layer and the third metal layer.

10. A semiconductor device comprising:
a semiconductor substrate;
a first metal layer provided above the semiconductor substrate;
a second metal layer provided above the first metal layer and containing Ni as a material;
a third metal layer provided above the second metal layer and containing Cu or Ni as a material; and
a resin layer provided on a part of an upper surface of the first metal layer and covered with the second metal layer, wherein
the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and
the third metal layer is harder than the first metal layer.

11. The semiconductor device according to claim 10 , wherein the resin layer is provided immediately below a region subjected to wire bonding.

12. The semiconductor device according to claim 1 , further comprising an antioxidant film provided above the third metal layer.

13. The semiconductor device according to claim 12 , further comprising a wire that penetrates the antioxidant film and is electrically connected to the third metal layer.

14. The semiconductor device of claim 13 , wherein the wire contains Cu as a material.

15. The semiconductor device according to claim 1 , further comprising a wire electrically connected to the third metal layer and containing Cu as the material.

16. The semiconductor device according to claim 1 , further comprising solder provided above the third metal layer.

17. The semiconductor device according to claim 1 , further comprising
a fifth metal layer provided under the semiconductor substrate;
a sixth metal layer provided under the fifth metal layer and containing Ni as a material; and
a seventh metal layer provided under the sixth metal layer and containing Cu or Ni as a material,
wherein the sixth metal layer has a Vickers hardness of 400 Hv or more and is harder than the seventh metal layer, and
the seventh metal layer is harder than the fifth metal layer.

18. The semiconductor device according to claim 1 , wherein the semiconductor substrate is made with a wide band gap semiconductor.

19. The semiconductor device according to claim 18 , wherein the wide band gap semiconductor is silicon carbide, gallium-nitride-based material or diamond.

20. A method for manufacturing a semiconductor device, the method comprising:
forming a first metal layer above a semiconductor substrate;
forming a second metal layer that contains Ni as a material above the first metal layer by plating; and
forming a third metal layer that contains Cu or Ni as a material above the second metal layer, wherein
the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer,
the third metal layer is harder than the first metal layer, and
the second metal layer directly contacts the first metal layer.

Assignees

• Mitsubishi Electric Corp

Inventors

• Tanaka Koji
• Sato Yuji
• Uchida Yoshihisa
• Nakamura Shotaro

Classifications

• H10P14/6928

  the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title