Storage device for backing up state group data in the event of a sudden power-off and program method thereof

Patent metadata

Field	Value
Publication number	US-12417814-B2
Application number	US-202318186480-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Oct 7, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Example embodiments are directed to a method for programming a storage device including a nonvolatile memory device and a storage controller for storing multi-bit data, programming, by the storage controller, the multi-bit data into the nonvolatile memory device based on a pre-programming operation, reading state group data of the multi-bit data generated in the nonvolatile memory device based on a program result of the pre-programming operation, and performing, by the storage controller, error correction decoding on the state group data.

First claim

What is claimed is:

1. A method for programming a storage device including a nonvolatile memory device and a storage controller for storing multi-bit data:
programming, by the storage controller, the multi-bit data into the nonvolatile memory device based on a pre-programming operation;
reading state group data of the multi-bit data generated in the nonvolatile memory device based on a program result of the pre-programming operation, the state group data including a data portion and a parity portion;
performing, by the storage controller, error correction decoding on the state group data, wherein the error correction decoding is performed based at least in part on the parity portion; and
removing the parity portion of the state group data after performing the error correction decoding.

2. The method of claim 1 , further comprising:
selectively inverting the state group data read based on multi-information.

3. The method of claim 2 , wherein the multi-information includes at least one of a number of bits of the multi-bit data, location information of a word line from which the multi-bit data being read, and a number of XOR operations used while generating the state group data.

4. The method of claim 3 , wherein in the selectively inverting, in response to a number of bits of the multi-bit data being even, the storage controller is configured to invert the read state group data, and in response to the number of bits of the multi-bit data being odd, the storage controller is configured to not invert the read state group data.

5. The method of claim 1 , further comprising:
backing up the state group data processed by the error correction decoding in the nonvolatile memory device in response to a sudden power-off event being detected.

6. The method of claim 5 , further comprising:
reading the multi-bit data based on the backed-up state group data in response to power being restored after the sudden power-off event; and
re-programming the read multi-bit data into the nonvolatile memory device.

7. The method of claim 6 , wherein a re-program verification voltage applied to any one program state in the re-programming is higher than a pre-program verification voltage applied to any one program state.

8. A storage device, comprising:
a nonvolatile memory device provided as a storage medium of the storage device;
a buffer memory configured to temporarily store data input/output to the nonvolatile memory device; and
a storage controller configured to perform a pre-program operation to program multi-bit data requested to be written into a first area of the nonvolatile memory device, and perform a re-program operation to program the multi-bit data into a second area of the nonvolatile memory device using a state group data generated through the pre-program operation, wherein the state group data includes a data portion and a parity portion,
the storage controller is further configured to perform error correction
decoding in response to reading the state group data and remove the parity portion of the state group data after performing the error correction decoding, and
the error correction decoding is performed based at least in part on the parity portion.

9. The storage device of claim 8 , wherein the storage controller comprises,
a power loss prevention circuit configured to detect a sudden power-off event;
a program manager configured to perform the pre-program operation and the re-program operation on the multi-bit data; and
an error correction code circuit configured to perform an error correction operation on the multi-bit data and the state group data,
wherein the error correction code circuit configured to perform a selective inversion operation on the read state group data.

10. The storage device of claim 9 , wherein the error correction code circuit comprises,
a first inverter configured to invert the state group data;
a multiplexer configured to select one of a non-inverted state group data and the state group data inverted by the first inverter based on multi-information;
a decoder configured to perform error correction decoding on the inverted or non-inverted state group data output from the multiplexer;
a second inverter configured to invert a data portion of the decoded inverted or non-inverted state group data and providing the decoded inverted or non-inverted state group data having the inverted data portion to the buffer memory; and
an inversion controller configured to control the multiplexer based on the multi-information.

11. The storage device of claim 10 , wherein the inversion controller includes a control logic or table configured to control the multiplexer based on a position of a word line from which the multi-bit data is read.

12. The storage device of claim 10 , wherein the inversion controller is configured to control the multiplexer to select an output of the first inverter in response to a number of bits of the multi-bit data being even, and to select the non-inverted state group data in response to the number of bits of the multi-bit data being odd.

13. The storage device of claim 10 , wherein the storage controller is configured to perform an error correction encoding operation on the data portion of the state group data and back up the data portion of the state group data to the nonvolatile memory device in response to the sudden power-off event occurring.

14. A programming method of a storage device storing multi-bit data based on a pre-program operation and a re-program operation:
programming the multi-bit data into a nonvolatile memory device based on the pre-program operation;
reading state group data of the multi-bit data generated based on the pre-program operation, wherein the state group data includes a data portion and a parity portion;
performing error correction decoding on the state group data, and wherein the error correction decoding is performed based at least in part on the parity portion; and
backing up the state group data processed by the error correction decoding after processing an error correction encoding in the nonvolatile memory device, in response to sudden power-off being detected,
wherein the parity portion is removed from the state group data processed by the error correction decoding.

15. The method of claim 14 , wherein the reading the state group data includes selectively inverting the state group data.

16. The method of claim 15 , wherein in the selectively inverting includes, determining whether to invert the state group data by referring to at least one of a number of bits of the multi-bit data, position information of a word line from which the multi-bit data was read, and a number of times of exclusive OR (XOR) operations used when generating the state group data.

17. The method of claim 16 , wherein, in response to the number of bits of the multi-bit data being an even number, the read state group data is inverted, and in response to the number of bits of the multi-bit data being an odd number, the state group data is non-inverted.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyeonwu
• Jo Hojun
• Mun Jihwan
• Lee Yoonjin
• Jang Jae Hun

Classifications

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1032

  Simple parity · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title