Method for accessing flash memory module and associated flash memory controller and memory device

Patent metadata

Field	Value
Publication number	US-10289487-B2
Application number	US-201715495993-A
Country	US
Kind code	B2
Filing date	Apr 25, 2017
Priority date	Apr 27, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

First claim

What is claimed is:

1. A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the method comprises:
encoding data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips;
writing the data into the first super block; and
writing the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;
wherein the at least one parity check code is a temporary parity check code, and the method further comprises:
reading the at least one parity check code from the second super block, and generating a final parity check code according to the at least one parity check code; and
writing the final parity check code into the first super block.

2. The method of claim 1 , further comprising:
before the data is written into the first super block, encoding the data to generate the at least one parity check code, and storing the at least one parity check code into a buffer memory of a flash memory controller; and
when error(s) occur due to writing procedure for the data or program fails, directly using the at least one parity check code stored in the buffer memory to correct the error(s) of the data.

3. The method of claim 1 , further comprising:
during the data being written into the super block:
reading a portion of the data, which has been written into the first super block, from the first super block; and
reading at least one portion of the parity check code from the second super block, and using the at least one portion of the parity check code to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data.

4. The method of claim 1 , wherein the step of performing encoding upon the data to generate the at least one parity check code comprises:
sequentially encoding 1 st -N th data units to generate 1 st -N th parity check codes, respectively; and
the step of writing the data into the first super block comprises:
respectively writing the 1 st -N th data units into 1 st -N th data pages corresponding to the flash memory chips of the first super block; and

the step of writing the at least one parity check code into the second super block comprises:
writing the 1 st -N th parity check codes into the second super block.

5. The method of claim 1 , wherein the at least one parity check code is a temporary parity check code, and the method further comprises:
reading the 1 st -N th parity check codes from the second super block, and generating a plurality of final parity check codes according to the 1 st -N th parity check codes; and
writing the plurality of final parity check codes into the first super block.

6. The method of claim 5 , wherein multiple word lines positioned on a same plane of each block forms a word line set, and the step of writing the plurality of final parity check codes into the first super block comprises:
writing the plurality of final parity check codes into data pages of a flash memory chip corresponding to last two word line sets of the first super block.

7. The method of claim 6 , wherein P th -N th data units are also written into the data pages of the flash memory chip corresponding to the last two word line sets of the first super block.

8. The method of claim 6 , further comprising:
after the final parity check code is written into the first super block, erasing contents of the second super block or marking the second super block as invalid/ineffective even if the data stored in the first super block is valid/effective.

9. The method of claim 1 , wherein the multiple-level cell blocks are triple-level cell (TLC) blocks or quad-level cell (QLC) blocks.

10. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:
a memory, for storing a program code;
a microprocessor, for executing the program code to control access of the flash memory module; and
a codec;
wherein the codec encodes data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and the microprocessor writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;
wherein during the data being written into the super block: the microprocessor reads a portion of the data, which has been written into the first super block, from the first super block; and the microprocessor reads at least one portion of the parity check code from the second super block, and uses the at least one portion of the parity check code to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data.

11. The flash memory controller of claim 10 , wherein before the data is written into the first super block, the codec encodes the data to generate the at least one parity check code, and stores the at least one parity check code into a buffer memory of a flash memory controller; and when error(s) occur due to writing procedure for the data or program fails, the codec directly uses the at least one parity check code stored in the buffer memory to correct the error(s) of the data.

12. The flash memory controller of claim 10 , wherein the at least one parity check code is a temporary parity check code, and the microprocessor reads the at least one parity check code from the second super block, and the codec generates a final parity check code according to the at least one parity check code, and the microprocessor writes the final parity check code into the first super block.

13. The flash memory controller of claim 10 , wherein the codec sequentially encodes 1 st -N th data units to generate 1 st -N th parity check codes, respectively, and respectively writes the 1 st -N th data units into 1 st -N th data pages corresponding to the flash memory chips of the first super block; and the microprocessor writes the 1 st -N th parity check cod

Assignees

• Silicon Motion Inc

Inventors

• Yang Tsung-Chieh
• Hsu Hong-Jung

Classifications

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G06F3/064

  Management of blocks · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title