Floating point to fixed point conversion

Patent metadata

Field	Value
Publication number	US-12417073-B2
Application number	US-202318104719-A
Country	US
Kind code	B2
Filing date	Feb 1, 2023
Priority date	Mar 24, 2017
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2 ew−1 −1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1), bitwidth(iw−2−s y )}≤k≤(ew−1) where s y =1 for a signed floating point number and s y =0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

First claim

What is claimed is:

1. A binary logic circuit for converting a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2 ew−1 −1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the binary logic circuit comprising:
a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein k is dependent on the integer width iw or the fractional width fw; and
a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

2. The binary logic circuit as claimed in claim 1 , wherein the binary logic circuit further comprises a formatting hardware circuit coupled to the shifter, the formatting hardware circuit configured to receive as an input a string comprising the mw mantissa bits and to format the string to generate the significand input to the shifter.

3. The binary logic circuit as claimed in claim 2 , wherein the formatting hardware circuit is configured to perform one or more formatting operations comprising appending (iw−2−s y ) bits to the most significant bit of the significand, where s y =0 and the appended bits are zero bits for an unsigned floating point number, and s y =1 and the appended bits are sign bits for a signed floating point number.

4. The binary logic circuit as claimed in claim 1 , wherein the input of the multiplexer is equal to the shifter output.

5. The binary logic circuit as claimed in claim 1 , wherein the shifter has a bit width equal to iw″+min(mw,(fw+iw″)), where iw″=min{(iw−2−s y ), 2 ew−1 −2}, wherein s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

6. The binary logic circuit as claimed in claim 2 , wherein the formatting hardware circuit is configured to perform one or more formatting operations comprising appending (iw−1−s y ) bits to the most significant bit of the significand, where s y =0 and the appended bits are zero bits for an unsigned floating point number, and s y =1 and the appended bits are sign bits for a signed floating point number.

7. The binary logic circuit as claimed in claim 1 , further comprising a correction hardware circuit coupled to the shifter and the multiplexer, the correction hardware circuit being configured to receive the shifter output and to discard its most significant bit and append a zero-bit to its least significant bit to form the input to the multiplexer.

8. The binary logic circuit as claimed in claim 1 , wherein the shifter has a bit width equal to iw′+min(mw, (fw+iw′)), where iw′=min{(iw−1−s y ), 2 ew−1 −1}, wherein s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

9. The binary logic circuit as claimed in claim 2 , wherein the formatting hardware circuit is further configured to truncate a set of least significant bits of the mw mantissa bits that would not form part of the fw bits of the fixed point format if left-shifted by a value equal to the shift range of the shifter.

10. The binary logic circuit as claimed in claim 1 , wherein the shifter has a shift range limited to the minimum of: i) iw−2−s y ; and ii) 2 ew−1 −2, wherein s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

11. The binary logic circuit as claimed in claim 1 , wherein the floating point format and fixed point format are such that (iw−s y −1)<2 ew−1 −1, and k is equal to the bit width of the value (iw−s y −2); or the floating point format and fixed point format are such that 2 ew−1 −1≤(iw−s y −1), and k=ew−1, where s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

12. The binary logic circuit as claimed in claim 1 , wherein the binary logic circuit further comprises an inverting hardware circuit configured to invert the bit values of the exponent; and an additional shifter coupled to the inverting hardware circuit configured to receive an additional significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the additional significand input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate an additional shifter output, wherein p is dependent on the integer width iw or the fractional width fw.

13. The binary logic circuit as claimed in claim 12 , further comprising an additional formatting hardware circuit coupled to the additional shifter, the additional formatting hardware circuit configured to receive as an input a string comprising the mw mantissa bits and to format the string to generate the additional significand input to the additional shifter.

14. The binary logic circuit as claimed in claim 12 , wherein the additional shifter has a bit width equal to: (1+s y )+min(fw, mw+2 ew−1 −2), wherein s y =1 for a signed floating point number and s y =0 for an unsigned floating point number.

15. The binary logic circuit as claimed in claim 12 , wherein the additional shifter has a shift range limited to the minimum of: i) 2 ew−1 −2; and ii) fw.

16. The binary logic circuit as claimed in claim 12 , further comprising a further formatting hardware circuit coupled to the additional shifter, the further formatting hardware circuit being configured to append (iw−1−s y ) bits to the most significant bit of the additional shifter output, where s y =0 and the appended bits are zero bits for an unsigned floating point number, and s y =1 and the appended bits are sign bits for a signed floating point number.

17. The binary logic circuit as claimed in claim 12 , wherein the floating point format and fixed point format are such that fw<2 ew−1 −1 and p is equal to the bit width to represent fw, or the floating point and fixed point numbers are such that fw≥2 ew−1 −1 and p=ew−1.

18. The binary logic circuit as claimed in claim 1 , wherein the binary logic circuit further comprises exception-handling circuitry configured to output an exception result in response to detecting an exception condition from a set of exception conditions comprising at least one of: i) E>B+iw−1−s y ; ii) E<B−fw, where s y =1 for a signed number and s y =0 for an unsigned number; and the binary logic circuit further comprises an output multiplexer configured to multiplex between the exception result and the output from the multiplexer coupled to the shifter.

19. A method of converting a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2 ew−1 −1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the method comprising:
receiving at a shifter a significand input comprising a contiguous set of the most significant bits of the significand and left-shifting the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein k is dependent on the integer width iw or the fractional width fw; and
receiving at a multiplexer an input comprising a contiguous set of bits of the shifter output and outputting the input if the most

Assignees

• Imagination Tech Ltd

Inventors

• Rovers Kenneth

Classifications

• G06F7/4824

  using signed-digit representation · CPC title

• H03M7/24 Primary

  Conversion to or from floating-point codes · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F5/012 Primary

  in floating-point computations · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title