Method for manufacturing an OxRAM-type resistive memory cell and associated OxRAM-type memory cell

Patent metadata

Field	Value
Publication number	US-12414485-B2
Application number	US-202418985575-A
Country	US
Kind code	B2
Filing date	Dec 18, 2024
Priority date	Dec 18, 2023
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A method for manufacturing an OxRAM resistive memory cell, includes forming a TiN lower electrode, firstly implanting Si atoms into the lower electrode with a first implantation dose and a first implantation acceleration voltage, the first implantation dose being strictly positive and strictly lower than 0.7·10 14 cm −2 , secondly implanting Si atoms into the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, the second implantation dose being strictly positive and strictly lower than 0.6·10 14 cm −2 , the first and second acceleration voltages being selected to have an implantation profile following the first and second implantations having a maximum Si concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode, depositing an active layer onto the lower electrode implanted, depositing an upper electrode onto the active layer.

First claim

What is claimed is:

1. A method for manufacturing an OxRAM-type resistive memory cell, comprising:
forming a titanium nitride lower electrode,
firstly implanting silicon atoms into the lower electrode with a first implantation dose of silicon and a first implantation acceleration voltage, said first implantation dose of silicon being strictly positive and strictly lower than 0.7×10 14 cm −2
secondly implanting silicon atoms into the lower electrode with a second implantation dose of silicon and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second implantation dose of silicon being strictly positive and strictly lower than 0.6·10 14 cm −2

the first and second acceleration voltages being selected to have an implantation profile following the first and second implantations having a maximum silicon concentration at a depth of between 1 and 3 nm from the upper surface of the lower electrode,
depositing an active layer onto the lower electrode implanted, and
depositing an upper electrode onto the active layer.

2. The method according to claim 1 , wherein the first and second acceleration voltages are selected to have an implantation profile following the first and second implantations having a maximum silicon concentration at a depth of between 1 and 1.6 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.6 nm and 2 nm.

3. The method according to claim 2 , wherein the first and second acceleration voltages are selected to have an implantation profile following the first and second implantations having a maximum silicon concentration at a depth of between 1.1 and 1.5 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.7 nm and 1.9 nm.

4. The method according to claim 1 , wherein depositing the upper electrode onto the active layer comprises:
depositing a first conductive layer, in contact with the active layer and being selected to create oxygen vacancies in the active layer, and
depositing a second conductive layer disposed onto the first conductive layer.

5. The method according to claim 4 , wherein the material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride.

6. The method according to claim 1 , wherein the first acceleration voltage is between 0.3 kV and 0.7 kV and the second acceleration voltage is between 1 kV and 2 kV.

7. The method according to claim 1 , wherein the first acceleration voltage is equal to 0.5 kV and the second acceleration voltage is equal to 1.5 kV.

8. The method according to claim 1 , wherein the first implantation dose of silicon is equal to 0.5·10 14 cm −2 and the second implantation dose of silicon is equal to 0.3·10 14 cm −2 .

9. The method according to claim 1 , wherein depositing the active layer onto the lower electrode implanted includes:
depositing an active material layer onto the lower electrode implanted,
depositing a dielectric oxide layer onto the active material layer,
implanting silicon atoms through the dielectric oxide layer, the implantation dose and the implantation acceleration voltage being selected so that the silicon atoms are implanted at least partially into the active material layer.

10. The method according to claim 9 , wherein the active material is based on hafnium dioxide.

11. The method according to claim 9 , wherein the dielectric oxide is based on aluminium oxide.

12. The method according to claim 6 , wherein implanting silicon through the dielectric oxide layer is implemented at an implantation acceleration voltage of between 1.5 and 3.5 kilovolts, and an implantation dose of silicon of between 10 15 cm −2 and 5·10 15 cm −2 .

13. The method according to claim 12 , wherein the implantation acceleration voltage is equal to 2.5 kV, and the implantation dose of silicon is equal to 2·10 15 cm −2 .

14. The method according to claim 1 , wherein a thickness of the titanium nitride lower electrode is selected between 10 and 200 nm.

15. An OxRAM-type memory cell obtained by the method according to claim 1 .

Assignees

• Commissariat Energie Atomique
• Weebit Nano Ltd

Inventors

• Molas Gabriel
• Verdy Anthonin
• Dory Jean-Baptiste
• Nodin Jean-François

Classifications

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/24 Primary

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10B63/00

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title

• H10N70/826 Primary

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title