Semiconductor device with a vertical channel wrapped around gate, and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12414288-B2
Application number	US-202217675838-A
Country	US
Kind code	B2
Filing date	Feb 18, 2022
Priority date	Feb 18, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A semiconductor device includes a transistor that is disposed on a substrate. The transistor includes a gate electrode located over the substrate, a gate dielectric disposed on the gate electrode, a channel layer disposed on the gate dielectric, a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate, and a second source/drain contact disposed on the channel layer and located on a side of the channel layer that faces the substrate. One of the gate dielectric and the channel layer at least partially surrounds the other one of the gate dielectric and the channel layer. A region of the channel layer between the first source/drain contact and the second source/drain contact is elongated in a direction perpendicular to the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising a transistor that is disposed on a substrate and that includes:
a bit line located over the substrate and extending in a first direction;
a gate electrode disposed above the bit line and extending in a second direction parallel to the substrate and perpendicular to the first direction;
a gate dielectric disposed on the gate electrode, and one of the gate electrode and the gate dielectric at least partially surrounding the other one of the gate electrode and the gate dielectric;
a channel layer disposed on the gate dielectric, and disposed above the bit line, one of the gate dielectric and the channel layer at least partially surrounding the other one of the gate dielectric and the channel layer;
a first source/drain contact disposed on the channel layer and located on a side of the channel layer that is opposite to the substrate; and
a second source/drain contact disposed on the channel layer and located on a bottom surface of the channel layer that faces the substrate;
wherein a region of the channel layer between the first source/drain contact and the second source/drain contact extends in a direction perpendicular to the substrate.

2. The semiconductor device of claim 1 , wherein the gate dielectric is formed on a top surface and sidewalls of the gate electrode to partially surround the gate electrode.

3. The semiconductor device of claim 2 , wherein the channel layer is formed on a top surface and sidewalls of the gate dielectric to partially surround the gate dielectric.

4. The semiconductor device of claim 3 , wherein the first source/drain contact is disposed on a top surface of the channel layer and is formed over the top surface of the gate electrode.

5. The semiconductor device of claim 4 , wherein the top surface of the channel layer has a dimension smaller than a dimension of a sidewall of the region of the channel layer between the first source/drain contact and the seconds source/drain contact.

6. The semiconductor device of claim 4 , wherein the first source/drain contact includes a bottom portion disposed on the top surface of the channel layer, and a top end connected to the bottom portion and distal from the channel layer, the top end having dimensions greater than those of the bottom portion.

7. The semiconductor device of claim 1 , further comprising a capacitor that is located over the transistor and that includes a capacitor electrode electrically connected to the first source/drain contact of the transistor, the capacitor and the transistor cooperating to form a one-transistor, one-capacitor (1T1C) memory cell.

8. The semiconductor device of claim 1 , wherein the second source/drain contact is located next to the gate electrode, is spaced apart from the gate electrode by the gate dielectric, and is in contact with a bottom portion of the channel layer that is adjacent to a foot of a sidewall of the gate electrode.

9. The semiconductor device of claim 1 , wherein the transistor is located over the bit line, and the second source/drain contact extends from the channel layer to the bit line and is electrically connected to the bit line.

10. The semiconductor device of claim 1 , wherein the gate dielectric covers a lateral side and portions of top and bottom sides of the gate electrode, and the channel layer is a U-shaped channel layer which covers a lateral side and top and bottom sides of the gate dielectric and is spaced apart from the gate electrode by the gate dielectric.

11. The semiconductor device of claim 1 , wherein a number of the gate dielectric is two and a number of the channel layer is two, the two gate dielectrics covering two lateral sides and portions of top and bottom sides of the gate electrode, the two channel layer being two U-shaped channel layers each of which covers a lateral side and top and bottom sides of a respective one of the gate dielectrics and is spaced apart from the gate electrode by the respective one of the gate dielectrics.

12. The semiconductor device of claim 1 , wherein the gate dielectric covers top, bottom and two lateral sides of the gate electrode, and the channel layer is an all-around channel layer which covers top, bottom and two lateral sides of the gate dielectric and is spaced apart from the gate electrode by the gate dielectric.

13. The semiconductor device of claim 1 , wherein the gate dielectric covers four lateral sides of the channel layer, and the gate electrode is an all-around gate electrode which covers four lateral sides of the gate dielectric and is spaced apart from the channel layer by the gate dielectric.

14. A semiconductor device comprising:
a substrate;
at least one bit line disposed on the substrate and extending in a first direction;
at least one gate feature extending in a second direction that is parallel to the substrate and substantially perpendicular to the first direction, and located over the bit line, a bottom surface of the at least one gate feature being disposed above a top surface of the at least one bit line;
at least one channel feature extending in the first direction and located over the gate feature, the at least one channel feature formed on a top surface and sidewalls of a segment of the at least one gate feature to cross over the at least one gate feature, the at least one channel feature disposed above the at least one bit line; and
at least one capacitor located over the at least one channel feature, and electrically connected to the at least one channel feature at a location where the at least one channel feature crosses over the at least one gate feature.

15. The semiconductor device of claim 14 , further comprising:
at least one connector contact disposed on the at least one channel feature at the location where the at least one channel feature crosses over the at least one gate feature, and interconnecting the at least one channel feature and a capacitor electrode of the at least one capacitor.

16. The semiconductor device of claim 14 , further comprising:
at least one via contact disposed on the at least one channel feature at a location beside the at least one gate electrode and distal from the at least one capacitor, and electrically connected to the at least one bit line located beneath the at least one channel feature.

17. The semiconductor device of claim 14 , further comprising:
at least one gate dielectric extending in the first direction, located over the at least one bit line and crossing over the at least one gate feature;
wherein the at least one channel feature is formed on the gate dielectric layer and is spaced apart from the at least one gate feature by the at least one gate dielectric.

18. A method for manufacturing a semiconductor device, comprising:
forming a conductive line in a substrate;
forming an interlayer dielectric (ILD) layer on the substrate formed with the conductive line;
forming a gate feature on the ILD layer, the gate feature extending parallel to the substrate and being substantially perpendicular to the conductive line;
forming a gate dielectric layer on the gate feature and the ILD layer, the gate dielectric layer disposed above the conductive line and crossing over the gate feature;
forming a via contact next to the gate feature in the gate dielectric layer and through the ILD layer for connection with the conductive line; and
forming a channel feature on the gate dielectric layer and the via contact, the channel feature disposed above the conductive line, partially surrounding the gate feature and being spaced apart from the gate f

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chieh
• Huang Chia-En
• Lee Chun-Ying

Classifications

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title