Error correction with error code for a string of symbols

Patent metadata

Field	Value
Publication number	US-12413250-B2
Application number	US-202318487267-A
Country	US
Kind code	B2
Filing date	Oct 16, 2023
Priority date	Oct 14, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation τ into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

First claim

What is claimed is:

1. A method for correcting errors in a string of symbols, comprising:
generating, via a processing unit, a codeword of a second error code from a codeword of a first error code;
storing, via the processing unit, the codeword of the second error code in a memory coupled to the processing unit;
reading, via the processing unit, bits from the memory, the bits corresponding to information included in the string of symbols;
detecting, via the processing unit, whether an error is present in the bits corresponding to the information included in the string of symbols based on whether the bits correspond to the codeword of the second error code;
generating, via the processing unit, a first group of symbols and a second group of symbols from the string of symbols in response to detecting the error, wherein the first group of symbols has fewer erroneous symbols than the second group of symbols; and
correcting, via the processing unit, the first group of symbols using the first error code.

2. The method of claim 1 , wherein the first error code is a byte-error-correcting error code.

3. The method of claim 2 , wherein the first error code is an N byte-error-correcting Reed-Solomon code over a Galois field GF(2 q ), where q is a number of bits of a symbol read out from the first group of symbols and the second group of symbols.

4. The method of claim 1 , wherein each of the symbols in the string of symbols comprises at least one of:
a byte,
a multi-valued component, or
a value from a specified value range.

5. The method of claim 1 , wherein the symbols comprise the codeword of the first error code.

6. The method of claim 5 , further comprising:
in response to detecting the error, generating the first group of symbols and the second group of symbols based on the codeword of the second error code.

7. The method of claim 5 , further comprising:
in response to detecting the error, generating the first group of symbols and the second group of symbols based on the codeword of the second error code, which has a distance of less than 3 positions from a nearest symbol of the erroneous symbols.

8. The method of claim 7 , wherein the codeword of the second error code, differs from an erroneous symbol by only one bit.

9. The method of claim 8 , the codeword of the second error code, has a minimum Hamming distance from the erroneous symbol.

10. The method of claim 1 , wherein the second error code is a parity code or an m-from-n code with 1≤m<n.

11. The method of claim 1 , wherein the string of symbols is transformed into the first group of symbols and into the second group of symbols, the first group of symbols being different from the second group of symbols, when a symbol of the string of symbols is not the codeword of the second error code and at least one error is present.

12. The method of claim 1 , further comprising:
determining a first error syndrome for the first group of symbols and a second error syndrome for the second group of symbols; and
determining whether the first group of symbols or the second group of symbols is corrected based on at least one of: the first error syndrome or the second error syndrome.

13. A computer program product, configured to be loaded directly into a memory of a digital computer, comprising program code configured to carry out the method of claim 1 .

14. A device for error correction in a string of symbols, comprising:
a memory;
at least one transformation circuit; and
a processor coupled to an input and an output of the memory and to the transformation circuit, the processor configured to:
generate, via the at least one transformation circuit, a codeword of a second error code from a codeword of a first error code;
store the codeword of the second error code in the memory;
read bits from the memory, the bits corresponding to information included in the string of symbols;
detect whether an error is present in the bits corresponding to the information included in the string of symbols based on whether the bits correspond to the codeword of the second error code;
generate, via the at least one transformation circuit, a first group of symbols and a second group of symbols from the string of symbols in response to detecting the error, wherein the first group of symbols comprises fewer errors than the second group of symbols; and
correct the first group of symbols based on the first error code.

15. The device for error correction as claimed in claim 14 , wherein the processor is further configured to generate, via the at least one transformation circuit, the first group of symbols and the second group of symbols based on a time domain and an error distance between the error and a nearest symbol of the codeword of the second error code.

16. A system for correcting errors in a string of symbols, the system comprising:
a memory;
at least one transformation circuit; and
a processor coupled to an input and an output of the memory and to the transformation circuit, the processor configured to:
read bits from the memory, the bits corresponding to information included in the string of symbols;
detect whether an error is present in binary data bits read from the memory based on whether the bits correspond to a codeword of a second error code stored in the memory, wherein the codeword of the second error code is derived from a codeword of a first error code;
generate, via the at least one transformation circuit, first symbols of a first q-bit byte and second symbols of a second q-bit byte from the string of symbols, in response to detecting the error, wherein q is equal to or greater than 2, and wherein the first symbols of the first q-bit byte comprise fewer erroneous symbols than the second symbols of the second q-bit byte; and
correct the first symbols of the first q-bit byte based on the first error code.

17. The system of claim 16 , wherein the processor is further configured to:
determine a first error syndrome for the first symbols of the first q-bit byte and a second error syndrome for the second symbols of the second q-bit byte; and
determine whether the first symbols of the first q-bit byte or the second symbols of the second q-bit byte are correctable based on at least one of: the first error syndrome or the second error syndrome.

18. The system of claim 16 , wherein the processor is further configured to:
determine whether the string of symbols comprises the codeword of the second error code or a non-codeword of the second error code based on the first symbols of the first q-bit byte and the second symbols of the second q-bit byte.

19. The system of claim 18 , wherein the processor is further configured to:
assign the string of symbols to a set of different codewords of the second error code in response to determining that the string of symbols is the non-codeword of the second error code.

20. The system of claim 16 , wherein the first error code comprises a Reed-Solomon code that corrects byte errors and the second error code comprises a parity code or an m-from-n code with 1≤m<n.

Assignees

• Infineon Technologies Ag

Inventors

• Kern Thomas
• Goessel Michael

Classifications

• H03M13/6516

  Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• H03M13/1515 Primary

  Reed-Solomon codes · CPC title

• H03M13/6502 Primary

  Reduction of hardware complexity or efficient processing · CPC title