Determining a state of a cell structure

Patent metadata

Field	Value
Publication number	US-9805771-B2
Application number	US-201414190435-A
Country	US
Kind code	B2
Filing date	Feb 26, 2014
Priority date	Feb 26, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.

First claim

The invention claimed is:

1. A method for determining a state of a cell structure, wherein the cell structure comprises several memory cells, comprising:
detecting a first condition in a predetermined number of memory cells of the cell structure and stopping a race condition in the time domain in response to the first condition detection;
assuming a second, different condition in the remaining cells of the cell structure where the first condition is not detected when the race condition was stopped; and
determining the state of the cell structure by assigning the second condition to the memory cells that do not show the first condition.

2. The method according to claim 1 , further comprising:
transforming electrical variables for each memory cell into a time domain; and
detecting the first condition in a predetermined number of memory cells by comparing the transformed electrical variables with a threshold.

3. The method according to claim 2 , wherein the threshold is adjustable.

4. The method according to claim 1 , wherein the first condition is a logic state corresponding to a logic “0” or a logic “1”.

5. The method according to claim 1 , wherein the second condition is a logic state corresponding to a logic “0” or a logic “1” and wherein the second condition is different from the first condition.

6. The method according to claim 1 , wherein the first condition is apparent sooner than the second condition and is determined prior to the second condition.

7. The method according to claim 1 , wherein the first condition corresponds to a first physical condition that can be detected earlier than a second physical condition that corresponds to the second condition.

8. The method according to claim 1 , wherein the cell structure comprises several complement cells.

9. The method according to claim 1 , wherein the memory cells are part of the same portion of memory.

10. The method according to claim 1 , wherein the several memory cells are represented by a group of at least two memory cells, and wherein at least two memory cells of this group are complementary cells of a differential read memory.

11. The method according to claim 10 , wherein the differential read memory comprises at least one of the following:
floating gate cells;
PCRAM,
RRAM,
MRAM,
MONOS devices,
nano crystal cells, and
ROM.

12. The method according to claim 1 , wherein the memory cells are memory cells of a non-volatile memory.

13. A device, comprising:
a memory comprising at least one cell structure, wherein the cell structure comprises several memory cells; and
a processing unit configured to:
detect a first condition in a predetermined number of memory cells of the at least one cell structure and stop a race condition in the time domain in response to the first condition detection;
assume a second, different condition in the remaining memory cells of the at least one cell structure where the first condition is not detected when the race condition was stopped; and
determine the state of the cell structure by assigning the second condition to the memory cells that do not show the first condition.

14. The device according to claim 13 , further comprising:
a conversion stage for transforming electrical variables for each memory cell into a time domain,
wherein the processing unit is arranged for detecting the first condition in a predetermined number of memory cells by comparing the transformed electrical variables with a threshold.

15. The device according to claim 14 , wherein the conversion stage is configured to transform the electrical variables into the time domain such that the first condition becomes apparent sooner than the second condition.

16. The device according to claim 13 , wherein the several memory cells are represented by a group of at least two memory cells, wherein at least two memory cells of this group are complementary cells of a differential read memory.

17. The device according to claim 16 , wherein the differential read memory comprises at least one of the following:
floating gate cells;
PCRAM,
RRAM,
MRAM,
MONOS devices,
nano crystal cells, and
ROM.

18. A computer program product stored in a non-transitory storage medium directly loadable into a memory of a digital processing device, comprising software code portions for performing the method according to claim 1 .

Assignees

• Infineon Technologies Ag

Inventors

• Loibl Ulrich
• Kern Thomas

Classifications

• G11C7/06 Primary

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C17/00

  Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards · CPC title

• G11C13/00

  Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 · CPC title