Methods and devices for increased efficiency in linear power amplifier

Patent metadata

Field	Value
Publication number	US-12413189-B2
Application number	US-202117358019-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A power amplifier circuit including a plurality of analog power amplifiers configured to generate a output power for an output signal; at least one processor configured to: select a highest output power signal; determine an input signal power of a modulated signal; determine an output signal power based on the input signal power; compare the output signal power and the highest output power; and disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

First claim

What is claimed is:

1. A power amplifier circuit comprising:
a plurality of analog power amplifiers configured to generate output signal power; and
at least one processor configured to:
select a highest output signal power;
determine an input signal power of a modulated signal, wherein the input signal power is based on a plurality of input signal user data symbols, wherein the plurality of input signal user data symbols include one or more resource blocks, wherein the input signal power is based on a count of the resource blocks in the plurality of input signal user data symbols, wherein the modulated signal comprises the plurality of input signal user data symbols;
determine an output signal power based on the input signal power;
compare the output signal power and the highest output signal power;
enable a power headroom; and
disable a subset of the plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power, wherein the output signal power includes the power headroom.

2. The circuit of claim 1 further comprising a parallel power amplifier block configured to generate the power headroom of up to ±1 dB.

3. The circuit of claim 1 further comprising an envelope detector, wherein the envelope detector is configured to receive an input signal; and
determine the input signal power based on the input signal.

4. The circuit of claim 1 wherein the plurality of analog power amplifiers are single stack power amplifiers.

5. The circuit of claim 4 wherein each of the plurality of single stack power amplifiers includes a switch; and wherein the one or more processors are configured to open the switch to disable the power amplifier.

6. The circuit of claim 1 wherein each of the plurality of analog power amplifiers includes a first power amplifier device and a second power amplifier device.

7. The circuit of claim 6 wherein the one or more processors are configured to selectively inject a gate voltage into each gate of the first power amplifier device or the second power amplifier device.

8. The circuit of claim 1 wherein each of the plurality of analog power amplifiers includes three or more power amplifier devices.

9. The circuit of claim 8 wherein the one or more processors are configured to selectively inject a gate voltage into each gate of one of the power amplifier devices.

10. The circuit of claim 1 further comprising a dummy power amplifier block, wherein the dummy power amplifier block is:
not connected to a load; and
connected to a power supply.

11. The circuit of claim 1 further including a harmonic trap, wherein the harmonic trap comprises:
a first inductor;
a second inductor; and
a capacitor operably coupled to the first inductor and the second inductor, wherein the capacitor is further connected to a reference signal.

12. A method for reducing static power consumption comprising:
selecting a highest output signal power;
determining an input signal power of a modulated signal based on a plurality of input signal user data symbols, wherein the plurality of input signal user data symbols include one or more resource blocks, wherein the input signal power is based on a count of the resource blocks in the plurality of input signal user data symbols, wherein the modulated signal comprises the plurality of input signal user data symbols;
determining an output signal power based on the input signal power;
comparing the output signal power and the highest output power; and
disabling a subset of a plurality of analog power amplifiers based on the comparison, wherein a remainder of the plurality of analog power amplifiers are configured to generate the output signal power.

13. The method of claim 12 further comprising:
enabling a power headroom; and
including the power headroom in the output signal power.

14. The method of claim 13 further comprising:
generating the power headroom of up to 1 dB.

15. The method of claim 13 further comprising:
receiving an input signal envelope; and
determining the input signal power based on the input signal envelope.

16. The method of claim 12 wherein the subset of the plurality of analog power amplifiers are single stack power amplifiers.

17. The method of claim 16 further comprising:
opening a tail switch of each of the subset of the plurality of analog power amplifiers.

Assignees

• Intel Corp

Inventors

• Azam Ali
• Ballantyne Wayne
• Chang Lichung

Classifications

• H03F1/3211

  in differential amplifiers · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F1/0277

  Selecting one or more amplifiers from a plurality of amplifiers · CPC title

• H03F2201/3215

  To increase the output power or efficiency · CPC title

• H03F2200/465

  Power sensing · CPC title