Front end systems and related devices, integrated circuits, modules, and methods

Patent metadata

Field	Value
Publication number	US-10276521-B2
Application number	US-201715857217-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 29, 2016
Publication date	Apr 30, 2019
Grant date	Apr 30, 2019

Abstract

Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. The low noise amplifier includes a first inductor, an amplification circuit, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.

First claim

What is claimed is:

1. A packaged module comprising:
a low noise amplifier within a package, the low noise amplifier including a first inductor, a series inductor having a first end configured to receive a radio frequency signal and a second end electrically connected to the first inductor, an amplification circuit configured to receive the radio frequency signal by way of the first inductor, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier; and
a multi-mode power amplifier circuit within the package, the multi-mode power amplifier circuit including a stacked output stage including a transistor stack of two or more transistors, and the multi-mode power amplifier circuit including a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit.

2. The packaged module of claim 1 further comprising a package substrate, a radio frequency shielding structure extending above the package substrate and enclosing the low noise amplifier and the multi-mode power amplifier circuit, and an antenna on the package substrate external to the radio frequency shielding structure.

3. The packaged module of claim 2 wherein the antenna is a multi-layer antenna.

4. The front end system of claim 1 further comprising a die supported by a package substrate and a crystal supported by the package substrate, the crystal being disposed between the die and the package substrate, and the die including the low noise amplifier and the multi-mode power amplifier.

5. A front end system comprising:
a low noise amplifier in a receive path of the front end system, the low noise amplifier including (i) an input matching circuit that includes a first inductor and a series inductor, the series inductor having a first end configured to receive a radio frequency signal and a second end electrically connected to the first inductor; (ii) an amplification circuit configured to receive the radio frequency by way of the first inductor; and (iii) a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier; and
a multi-mode power amplifier circuit in a transmit path of the front end system, the multi-mode power amplifier circuit including a stacked output stage including a transistor stack of two or more transistors, and the multi-mode power amplifier circuit including a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit.

6. The front end system of claim 5 wherein the bias circuit is configured to bias a transistor of the transistor stack to a linear region of operation in a first mode, and as a switch in a second mode.

7. The front end system of claim 6 wherein the bias circuit is configured to bias the transistor in a saturation region of operation in the second mode.

8. The front end system of claim 6 wherein the second mode is associated with a lower power than the first mode.

9. The front end system of claim 6 wherein the stacked output stage is configured to receive a supply voltage having a lower voltage level in the second mode relative to the first mode.

10. The front end system of claim 5 further comprising a supply control circuit configured to provide a supply voltage to the stacked output stage such that the supply voltage has a different voltage level in each of at least three different modes.

11. The front end system of claim 5 wherein the transistor stack includes at least three transistors in series.

12. The front end system of claim 10 wherein the multi-mode power amplifier circuit includes an input stage having an output electrically coupled to an input of the stacked output stage, and the supply control circuit is configured to provide an input stage supply voltage to the input state, the input stage supply voltage having a substantially constant voltage level in each of the three different modes.

13. The front end system of claim 5 further comprising a low noise amplifier bias circuit configured to apply a low noise amplifier bias signal at a node between the first inductor and the series inductor.

14. The front end system of claim 5 wherein the input matching circuit further includes a direct current blocking capacitor configured to provide the radio frequency signal to the series inductor.

15. The front end system of claim 5 wherein the second inductor is a degeneration inductor.

16. The front end system of claim 5 further comprising a radio frequency switch coupled to the low noise amplifier and the multi-mode power amplifier circuit.

17. The front end system of claim 16 wherein the radio frequency switch is configured to electrically couple an antenna port to the transmit path in a first state and to electrically couple the antenna port to the receive path in a second state.

18. A wireless communication device comprising:
a low noise amplifier in a receive path of a front end system, the low noise amplifier including a first inductor, a series inductor having a first end configured to receive a radio frequency signal and a second end electrically connected to the first inductor, an amplification circuit configured to receive the radio frequency signal by way of the first inductor, and a second inductor magnetically coupled to the first inductor to provide negative feedback to linearize the low noise amplifier;
a multi-mode power amplifier circuit in a transmit path of the front end system, the multi-mode power amplifier circuit including a stacked output stage including a transistor stack of two or more transistors, and the multi-mode power amplifier circuit including a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit;
an antenna; and
a radio frequency switch configured to electrically couple the antenna to the transmit path in a first state and to electrically couple the antenna to the receive path in a second state.

19. The wireless communication device of claim 18 wherein the low noise amplifier and the multi-mode power amplifier are embodied on a single semiconductor-on-insulator die.

20. The wireless communication device of claim 18 wherein the multi-mode power amplifier circuit is configured to output a wireless local area network signal for transmission via the antenna.

Assignees

• Skyworks Solutions Inc

Inventors

• Babcock Gregory Edward
• Deorio Lori Ann
• Frenette Darren Roger
• Khoury George
• Lobianco Anthony James
• Nguyen Hoang Mong
• Soliman Yasser Khairat
• Wallis Leslie Paul
• Rodríguez René

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title