Doherty amplifiers

Patent metadata

Field	Value
Publication number	US-12413187-B2
Application number	US-202218052586-A
Country	US
Kind code	B2
Filing date	Nov 4, 2022
Priority date	Aug 18, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A Doherty amplifier includes first and second input terminals, first and second amplifiers, and an output combiner circuit. The first amplifier includes a first amplifier input coupled to the first input terminal, and a first amplifier output. The second amplifier includes a second amplifier input coupled to the second input terminal, and a second amplifier output. The output combiner circuit is coupled between the first amplifier output, the second amplifier output, and a final summing node. The output combiner circuit includes a first inductive element, a first capacitor integrated within an integrated passive device (IPD), and a second inductive element. The first inductive element is coupled between the first amplifier output and a first terminal of the first capacitor, and the second inductive element is coupled between a combining node and the first terminal of the first capacitor. A second terminal of the first capacitor is coupled to ground.

First claim

The invention claimed is:

1. A Doherty amplifier device, comprising:
a first input terminal;
a second input terminal;
a third input terminal;
an integrated output combiner circuit comprising a first output network, a second output network, a third output network, an intermediate summing node, and a final summing node;
a carrier amplifier including a first amplifier input coupled to the first input terminal, and a first amplifier output coupled through the first output network to the final summing node, wherein the first output network includes a first inductive element in the form of a first set of wirebonds coupled between the first amplifier output and a first intermediate node, a second inductive element in the form of a second set of wirebonds coupled between the first intermediate node and the final summing node, and a first capacitor coupled between the first intermediate node and a ground plane;
a first peaking amplifier including a second amplifier input coupled to the second input terminal, and a second amplifier output, wherein the second amplifier output is directly coupled to the intermediate summing node, the second amplifier output and the intermediate summing node are coupled through the second output network to the final summing node, the second output network includes a third inductive element in the form of a third set of wirebonds coupled between the final summing node and a second intermediate node, a fourth inductive element in the form of a fourth set of wirebonds coupled between the second intermediate node and the intermediate summing node, and a second capacitor coupled between the second intermediate node and the ground plane; and
a second peaking amplifier including a third amplifier input coupled to the third input terminal, and a third amplifier output coupled through the third output network to the intermediate summing node, wherein the third output network includes a fifth inductive element in the form of a fifth set of wirebonds coupled between the intermediate summing node and a third intermediate node, a sixth inductive element in the form of a sixth set of wirebonds coupled between the third intermediate node and the third amplifier output, and a third capacitor coupled between the third intermediate node and the ground plane,
wherein the first output network imparts a phase delay of 90 degrees between an input of the first output network and an output of the first output network and provides a first impedance, the second output network imparts a phase delay of 90 degrees between an input of the second output network and an output of the second output network and provides a second impedance, and the third output network imparts a phase delay of 90 degrees between an input of the third output network and an output of the third output network and provides a third impedance.

2. The device of claim 1 , wherein the phase shift between the first amplifier input and the second amplifier input is 0°, and the phase shift between the second amplifier input and the third amplifier input is 90°.

3. The device of claim 1 , wherein the final summing node comprises an output terminal of the device.

4. The device of claim 1 , further comprising:
a conductive substrate, wherein the first, second, and third power transistors and the first, second, and third capacitors are coupled to a surface of the conductive substrate, and the conductive substrate corresponds to the ground plane; and
plastic molding compound applied over the first, second, and third power transistors.

5. The device of claim 1 , wherein the device is a packaged amplifier device that has a device type selected from a group consisting of a dual-flat no-leads device and a quad-flat no-leads device.

6. The device of claim 1 , wherein the first capacitor is integrated within a first integrated passive device (IPD), the second capacitor is integrated within a second IPD, and the third capacitor is integrated within a third IPD.

7. The device of claim 1 , wherein:
the device is a packaged amplifier device;
the first, second, and third terminals are first, second, and third leads of the packaged amplifier device;
the final summing node comprises an output terminal of the device; and
the output terminal corresponds to a fourth lead of the packaged amplifier device.

8. The device of claim 1 , further comprising a resonator coupled between the final summing node and the ground plane, wherein the resonator comprises a seventh inductive element and a fourth capacitor coupled in series, and the resonator is configured to resonate at a second harmonic frequency of a center frequency of operation of the device.

9. The device of claim 1 , wherein:
the carrier amplifier comprises a first input impedance matching network and a first power transistor, wherein the first input impedance matching network is configured to match an impedance between the first input terminal and the first power transistor;
the first peaking amplifier comprises a second input impedance matching network and a second power transistor, wherein the second input impedance matching network is configured to match an impedance between the second input terminal and the second power transistor; and
the second peaking amplifier comprises a third input impedance matching network and a third power transistor, wherein the third input impedance matching network is configured to match an impedance between the third input terminal and the third power transistor.

10. The device of claim 9 , wherein:
the first power transistor is a first field effect transistor with a first gate terminal coupled to the first input impedance matching network, a first drain terminal coupled to the first inductive element, and a first source terminal coupled to the ground plane,
the second power transistor is a second field effect transistor with a second gate terminal coupled to the second input impedance matching network, a second drain terminal coupled to the intermediate summing node, and a second source terminal coupled to the ground plane, and
the third power transistor is a third field effect transistor with a third gate terminal coupled to the third input impedance matching network, a third drain terminal coupled to the sixth inductive element, and a third source terminal coupled to the ground plane.

11. A Doherty amplifier, comprising:
a first input;
a second input;
a third input;
an output;
an output combiner circuit with first, second, and third combining network inputs, first, second, and third output networks, an intermediate summing node corresponding to the second combining network input, a final summing node, and a combining network output corresponding to the final summing node and coupled to the output directly;
a carrier amplifier including a first amplifier input coupled to the first input, and a first amplifier output coupled to the first combining network input;
a first peaking amplifier including a second amplifier input coupled to the second input, and a second amplifier output directly coupled to the second combining network input; and
a second peaking amplifier including a third amplifier input coupled to the third input, and a third amplifier output coupled to the third combining network input,
wherein the first output network includes a first inductive element in the form of a first set of wirebonds coupled between the first combining network input and a first intermediate node, a second inductive element in the form of a second set of wirebonds coupled between the first intermediate node and the combining network output, and a first capacitor coupled between the first intermediate node and a ground plane,
wherein the second output netw

Assignees

• Nxp Usa Inc

Inventors

• Hua Qi
• Wang Yunfei
• Wu Qi
• Wang Changyang

Classifications

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/231

  Arrangements for applying bias · CPC title

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/521

  Structures or relative sizes of bond wires · CPC title