Semiconductor package and memory device including the same

Patent metadata

Field	Value
Publication number	US-12412849-B2
Application number	US-202217899715-A
Country	US
Kind code	B2
Filing date	Aug 31, 2022
Priority date	Sep 3, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A semiconductor package includes: a package board including a plurality of connection pads; a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip contacts a first surface of the package board, and wherein the plurality of bonding pads are respectively connected to the plurality of connection pads; and a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package board including a plurality of connection pads;
a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip contacts a first surface of the package board, and wherein the plurality of bonding pads are respectively connected to the plurality of connection pads; and
a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

2. The semiconductor package of claim 1 , wherein the thermal fuse circuit is arranged on a second surface of the semiconductor chip.

3. The semiconductor package of claim 2 , wherein the thermal fuse circuit is arranged on the second surface of the semiconductor chip such that it is located in a central region of the package board.

4. The semiconductor package of claim 1 , wherein the sensing connection pad is one of the plurality of connection pads to which signals used in an internal operation of the semiconductor chip are transmitted, and the sensing bonding pad is one of the plurality of bonding pads to which signals used in the internal operation of the semiconductor chip are transmitted.

5. The semiconductor package of claim 4 , wherein the internal operation comprises a read operation of transmitting data stored in the semiconductor chip, and signals used in the read operation comprise a chip enable signal, a read enable signal, a data strobe signal, a data signal, and a power signal.

6. The semiconductor package of claim 1 , wherein the cutoff temperature is greater than a temperature obtained by adding a first margin temperature to a reflow process temperature.

7. The semiconductor package of claim 6 , wherein the cutoff temperature is less than a temperature obtained by adding a second margin temperature to the reflow process temperature, and the second margin temperature is greater than the first margin temperature.

8. The semiconductor package of claim 1 , wherein the thermal fuse circuit comprises:
a first thermal fuse having a first end connected to the sensing connection pad;
a second thermal fuse having a first end connected to the sensing connection pad; and
an AND gate having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to a second end of the first thermal fuse, wherein the second input terminal is connected to a second end of the second thermal fuse, and wherein the output terminal is connected to the sensing bonding pad.

9. The semiconductor package of claim 1 , wherein the thermal fuse circuit comprises:
a third thermal fuse having a first end connected to the sensing connection pad; and
a fourth thermal fuse having a first end and a second end, wherein the first end of the fourth thermal fuse is connected to a second end of the third thermal fuse, and the second end of the fourth thermal fuse is connected to the sensing bonding pad.

10. The semiconductor package of claim 1 , wherein, when the internal temperature is greater than or equal to the cutoff temperature regardless of a supply of power, the thermal fuse circuit opens between the sensing connection pad and the sensing bonding pad.

11. The semiconductor package of claim 1 , wherein the plurality of connection pads and the plurality of bonding pads are respectively connected to one another through a corresponding wire.

12. A semiconductor package comprising:
a package board including a plurality of connection pads;
a first semiconductor chip including a first surface and a plurality of first bonding pads, wherein the first surface of the first semiconductor chip is in contact with a first surface of the package board;
a second semiconductor chip including a first surface and a plurality of second bonding pads, wherein the first surface of the second semiconductor chip is in contact with a second surface of the first semiconductor chip, and wherein the plurality of second bonding pads are connected to the plurality of connection pads and the plurality of first bonding pads; and
a thermal fuse circuit connected between a sensing connection pad of the plurality of connection pads and a second sensing bonding pad of the plurality of second bonding pads, and configured to open between the sensing connection pad and the second sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

13. The semiconductor package of claim 12 , wherein the thermal fuse circuit is arranged on a second surface of the second semiconductor chip such that it is located in a central region of the package board.

14. The semiconductor package of claim 12 , wherein the second sensing bonding pad is connected to a first sensing bonding pad of the plurality of first bonding pads.

15. The semiconductor package of claim 14 , wherein the sensing connection pad is one of the plurality of connection pads to which signals used in an internal operation of the first semiconductor chip or the second semiconductor chip are transmitted, wherein the first sensing bonding pad is one of the plurality of first bonding pads to which signals used in an internal operation of the first semiconductor chip or the second semiconductor chip are transmitted, and wherein the second sensing bonding pad is one of the plurality of second bonding pads to which signals used in an internal operation of the first semiconductor chip or the second semiconductor chip are transmitted.

16. The semiconductor package of claim 12 , wherein the plurality of connection pads and the plurality of first bonding pads are respectively connected to one another through a corresponding wire, and the plurality of first bonding pads and the plurality of second bonding pads are respectively connected to one another through a corresponding wire.

17. A memory device comprising:
a circuit board comprising a plurality of connection pins;
a package board including a plurality of connection pads to be connected to the plurality of connection pins through a plurality of solder balls;
a semiconductor chip including a first surface and a plurality of bonding pads, wherein the first surface of the semiconductor chip is in contact with a first surface of the package board, and wherein the plurality of bonding pads are connected to the plurality of connection pads; and
a thermal fuse circuit connected to a sensing connection pad of the plurality of connection pads and a sensing bonding pad of the plurality of bonding pads, and configured to open between the sensing connection pad and the sensing bonding pad when an internal temperature of the thermal fuse circuit is greater than or equal to a cutoff temperature of the thermal fuse circuit.

18. The memory device of claim 17 , wherein the sensing connection pad is connected to a sensing connection pin of the plurality of connection pins, wherein the sensing connection pin is one of the plurality of connection pins to which signals used in an internal operation of the semiconductor chip are transmitted, wherein the sensing connection pad is one of the plurality of connection pads to which signals used in an internal operation of the semiconductor chip are transmitted, and wherein t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyunjin

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/758

  between a chip and a stacked discrete passive device · CPC title