Programmable hardware accelerator controller

Patent metadata

Field	Value
Publication number	US-12411696-B2
Application number	US-202318176323-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Dec 29, 2022
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.

First claim

The invention claimed is:

1. A device, comprising:
a hardware accelerator, comprising a plurality of registers:
a memory; and
a configuration controller coupled to the hardware accelerator and to the memory, wherein the configuration controller, in operation, executes a finite state machine, wherein the finite state machine controls execution of a linked list of configuration operations, the linked list of configuration operations consisting of configuration operations selected from a defined set of configuration operations, wherein the executing the linked list of configuration operations configures the plurality of registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of a multi-stage processing task, wherein the configuration controller, in operation, retrieves a binary blob from the memory, the binary blob including the linked list of configuration operations.

2. The device of claim 1 , wherein the finite state machine comprises a wait state, a load list state and an execute configuration operation state.

3. The device of claim 2 , wherein the finite state machine comprises a decryption state and a validity check state.

4. The device of claim 1 , wherein the binary blob comprises a plurality of configuration words and the configuration operations of the linked list of configuration operations are included in respective configuration words of the plurality of configuration words.

5. The device of claim 4 , wherein the plurality of configuration words include words storing control parameters or data associated with configuration operations of the linked list of configuration operations.

6. The device of claim 1 , wherein the linked list of configuration operations includes more than one instance of an operation selected from the defined set of configuration operations.

7. The device of claim 1 , wherein the plurality of registers comprises a plurality of configuration registers.

8. A system, comprising
a host processor, which, in operation, controls execution of a multi-stage processing task;
a memory, which, in operation, stores data and configuration information;
a hardware accelerator, the hardware accelerator including:
a plurality of functional circuits; and
a plurality of configuration registers; and
a configuration controller coupled to the host processor, the hardware accelerator, and the memory, wherein the configuration controller, in operation:
executes a finite state machine to control execution of a linked list of configuration operations, the linked list of configuration operations consisting of configuration operations selected from a defined set of configuration operations, wherein the executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task, wherein the configuration controller, in operation, retrieves a binary blob from the memory, the binary blob including the linked list of configuration operations.

9. The system of claim 8 , wherein the configuration controller comprises cryptographic circuitry, and the cryptographic circuitry, in operation, decrypts words of the binary blob retrieved from the memory.

10. The system of claim 8 , comprising a configuration bus and a data bus, wherein the configuration controller, in operation:
responds to an indication to retrieve the binary blob received from the host processor via the configuration bus by retrieving the binary blob from the memory via the data bus.

11. The system of claim 10 , wherein the data bus is a streaming data bus.

12. The system of claim 10 , wherein the configuration controller, in operation:
waits for an indication to execute the retrieved linked list of configuration operations; and
responds to an indication to execute the linked list of configuration operations received from the host processor via the configuration bus by executing the linked list of configuration operations.

13. The system of claim 8 , wherein the binary blob comprises a plurality of configuration words and the configuration operations of the linked list of configuration operations are included in respective configuration words of the plurality of configuration words.

14. A method, comprising:
retrieving, by a configuration controller from a memory, configuration operations of a linked list of configuration operations, the linked list of configuration operations consisting of configuration operations selected from a defined set of configuration operations; and
executing, under control of a finite state machine executed by the configuration controller, the retrieved configuration operations of the linked list of configuration operations, the executing of the retrieved configuration operations of the linked list of configuration operations configuring a plurality of registers of a hardware accelerator to control operations of the hardware accelerator associated with a stage of a multi-stage processing task controlled by a host processor, wherein the method comprises retrieving a binary blob from the memory, the binary blob including the linked list of configuration operations.

15. The method of claim 14 , comprising decrypting the binary blob.

16. The method of claim 14 , comprising verifying a validity of the linked list of configuration operations prior to executing the linked list of configuration operations.

17. A non-transitory computer-readable medium having contents which cause a configuration controller to perform a method, the method comprising:
sequentially executing individual operations of a linked list of configuration operations under control of a finite state machine executed by the configuration controller, the linked list of configuration operations consisting of configuration operations selected from a defined set of configuration operations, the executing of the linked list of configuration operations configuring a plurality of registers of a hardware accelerator to control operations of the hardware accelerator associated with a stage of a multi-stage processing task controlled by a host processing system, wherein the contents comprise a binary blob including the linked list of configuration operations.

18. The non-transitory computer-readable medium of claim 17 , wherein the method comprises retrieving the binary blob from a memory of the host processing system.

Assignees

• St Microelectronics Srl
• St Microelectronics Int Nv

Inventors

• Zambotti Paolo Sergio
• Boesch Thomas
• Desoli Giuseppe
• Betz Wolfgang Johann
• Siorpaes David

Classifications

• G06F9/5038

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F9/4498

  Finite state machines · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F15/7889

  Reconfigurable logic implemented as a co-processor (instruction execution using a coprocessor G06F9/3877) · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title