Programmable hardware accelerators in CPU

Patent metadata

Field	Value
Publication number	US-9880852-B2
Application number	US-201213728904-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Dec 27, 2012
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware accelerator, and a controller programmed to monitor the instruction queue to detect a first type of instructions stored in the instruction queue, reprogram the programmable hardware accelerator to execute the first type of instructions, and transmit the first type of instructions to the programmable hardware accelerator to be executed.

First claim

What is claimed is:

1. A processing system comprising:
an instruction queue to store instructions;
a hardware-accelerator execution unit; and
a controller programmed to:
monitor the instruction queue to detect that a number of instructions of a first type stored in the instruction queue exceed a particular threshold;
reprogram the hardware-accelerator execution unit to execute the instructions of the first type based on the number exceeding the particular threshold; and
transmit the instructions of the first type to the hardware-accelerator execution unit to be executed.

2. The processing system of claim 1 , wherein the controller is further programmed to:
detect a second type of the instructions in the instruction queue,
reprogram the hardware-accelerator execution unit to execute the instructions of the second; and
transmit the instructions of the second type to the hardware-accelerator execution unit to be executed.

3. The processing system of claim 1 , wherein a field-programmable gate array includes the hardware-accelerator execution unit.

4. The processing system of claim 2 , wherein:
the instructions of the first type comprise addition operations and the controller is further programmed to reprogram the hardware-accelerator execution unit to execute the addition operations; and
the instructions of the second type comprise multiplication operations and the controller is further programmed to reprogram the hardware-accelerator execution unit to execute the multiplication operations.

5. The processing system of claim 1 , wherein a programmable hardware accelerator includes the hardware-accelerator execution unit.

6. The processing system of claim 1 , further comprising an additional programmable hardware accelerator that includes an additional hardware-accelerator execution unit;
wherein the controller reprograms the additional hardware-accelerator execution unit to execute the first type of instructions.

7. The processing system of claim 6 , wherein the controller is further programmed to:
in a first operation mode, power off the programmable hardware accelerator and the additional programmable hardware accelerator;
in a second operation mode, power on the programmable hardware accelerator and power off the additional programmable hardware accelerator; and
in a third operation mode, power on the programmable hardware accelerator and the additional programmable hardware accelerator.

8. The processing system of claim 7 , wherein the controller is further programmed to select a mode of operation based on a number of instructions to be executed by the programmable hardware accelerator and the additional programmable hardware accelerator.

9. An apparatus comprising:
a processor comprising an instruction queue, a controller, and a hardware-accelerator execution unit, the processor to execute instructions stored in the instruction queue, wherein the processor is configured to:
monitor, using a controller, the instruction queue to detect that a number of instructions of a first type stored in the instruction queue exceed a particular threshold;
reprogram, using the controller, a hardware-accelerator execution unit to execute the instructions of the first type based on the number exceeding the particular threshold; and
transmit, using the controller, the instructions of the first type to the hardware-accelerator execution unit to be executed.

10. The apparatus of claim 9 , wherein the controller is programmed to:
detect a second type of the instructions stored in the instruction queue;
reprogram the hardware-accelerator execution unit execute the second type of instructions; and
transmit the instructions of the second type to the hardware-accelerator execution unit to be executed.

11. The apparatus of claim 9 , wherein a field-programmable gate array includes the hardware-accelerator execution unit.

12. The apparatus of claim 10 , wherein:
the instructions of the first type comprise addition operations and the controller is further programmed to reprogram the hardware-accelerator execution unit to execute the addition operations; and
the second type of the instructions comprise multiplication operations and the controller is further programmed to reprogram the hardware-accelerator execution unit to execute the multiplication operations.

13. The processing apparatus of claim 9 , wherein a programmable hardware accelerator includes the hardware-accelerator execution unit.

14. The apparatus of claim 13 , further comprising an additional of programmable hardware accelerator that includes an additional hardware-accelerator execution unit;
wherein the controller reprogram the additional hardware-accelerator execution unit to execute the first type of instructions.

15. The apparatus of claim 14 , wherein the controller is further programmed to:
in a first operation mode, power off the programmable hardware accelerator and the additional programmable hardware accelerator;
in a second operation mode, power on the programmable hardware accelerator and power off the additional programmable hardware accelerator; and
in a third operation mode, power on the programmable hardware accelerator and the additional programmable hardware accelerator.

16. The apparatus of claim 15 , wherein the controller selects from the first, second, and third modes of operation based on a number of instructions to be executed by the programmable hardware accelerator and the additional programmable hardware accelerator.

17. An apparatus comprising:
a processor to execute a portion of instructions stored in an instruction queue using an execution, unit; and
a programmable hardware accelerator including a hardware-accelerator controller and a hardware-accelerator execution unit, the hardware-accelerator controller programmed to:
monitor the instruction queue to detect that a number of instructions of a first type stored in the instruction queue exceed a particular threshold;
reprogram the hardware-accelerator execution unit to execute the instructions of the first type based on the number exceeding the particular threshold; and
transmit the instructions of the first type to the hardware-accelerator execution unit to be executed.

18. The apparatus of claim 17 , wherein the hardware-accelerator controller is programmed to:
detect instructions of a second type stored in the instruction queue;
reprogram the hardware-accelerator execution unit to execute the instructions of a second type; and
transmit the instructions of the second type to the hardware-accelerator execution unit to be executed.

19. The apparatus of claim 17 , wherein is a field-programmable gate array includes the hardware-accelerator execution unit.

20. The apparatus of claim 18 , wherein:
the instructions of the first type comprise addition operations and the hardware-accelerator controller is further programmed to reprogram the hardware-accelerator execution unit to execute the addition operations; and
the instructions of the second type comprise multiplication operations and the hardware-accelerator controller is further programmed to reprogram the hardware-accelerator execution unit to execute the multiplication operations.

21. The apparatus of claim 17 , wherein the programmable hardware accelerator is powered off when the hardware-accelerator execution unit is not executing instructions.

22. A method comprising:
monitoring, by a controller, instructions stored in an instruction queue, w

Assignees

• Intel Corp

Inventors

• Tan Kia Leong

Classifications

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F9/48

  Program initiating; Program switching, e.g. by interrupt · CPC title

• G06F9/3881 Primary

  Arrangements for communication of instructions and data · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title