LDO circuit having power supply rejection function, chip and communication terminal

Patent metadata

Field	Value
Publication number	US-12411509-B2
Application number	US-202418423207-A
Country	US
Kind code	B2
Filing date	Jan 25, 2024
Priority date	Jul 30, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

An LDO circuit having a power supply rejection function, a chip, and a communication terminal. The LDO circuit includes a bandgap reference module provided with an intermediate frequency zero adjustment unit, an amplification module provided with an intermediate frequency zero generation unit, and a power output module. The bandgap reference module is connected to the amplification module, and the amplification module is connected to the power output module. For the purpose of power supply rejection at an intermediate frequency, the intermediate frequency zero adjustment unit in the bandgap reference module and the intermediate frequency zero generation unit in the LDO circuit are adjusted in coordination to better optimize the intermediate frequency power supply rejection performance.

First claim

What is claimed is:

1. An LDO circuit having a power supply rejection function, comprising a bandgap reference module provided with an intermediate frequency zero adjustment unit, an amplifier module provided with an intermediate frequency zero generation unit, and a power output module,
wherein the bandgap reference module is connected to the amplifier module, and the amplifier module is connected to the power output module;
wherein the bandgap reference module generates a reference voltage having a preset temperature coefficient by using a frequency of an intermediate frequency zero adjusted by the intermediate frequency zero adjustment unit and outputs the reference voltage to the amplifier module, and the reference voltage is used as a voltage reference of the LDO circuit and works in coordination with a zero that is generated by the intermediate frequency zero generation unit and whose frequency is an intermediate frequency, to adjust power supply rejection of the LDO circuit at an intermediate frequency;
wherein the bandgap reference module comprises a starting unit, a PTAT current generation unit, an output unit, and the intermediate frequency zero adjustment unit, an output end of the starting unit and an output end of the intermediate frequency zero adjustment unit are connected to an input end of the PTAT current generation unit, an output end of the PTAT current generation unit is connected to an input end of the output unit, and an output end of the output unit is connected to an input end of the amplifier module;
wherein the starting unit comprises a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein a source of the first PMOS transistor and a source of the second PMOS transistor are connected to a power supply voltage; a drain of the second PMOS transistor is connected to one end of the first resistor; the other end of the first resistor is connected to a drain of the first PMOS transistor, a gate of the fourth PMOS transistor, and one end of the second resistor; the other end of the second resistor is connected to a gate and a drain of the first NMOS transistor; a drain of the fourth PMOS transistor is connected to a gate and a drain of the third NMOS transistor and a gate of the fourth NMOS transistor; a drain of the fourth NMOS transistor, a source of the fourth PMOS transistor, and a drain of the third PMOS transistor are connected to each other, and are connected to the PTAT current generation unit with a gate of the second PMOS transistor; a gate of the first PMOS transistor, a gate of the second NMOS transistor, and a gate of the third PMOS transistor each are connected to an external enable signal; the source of the first PMOS transistor, the source of the second PMOS transistor, and a source of the third PMOS transistor are connected to the power supply voltage; and a source of the second NMOS transistor, a source of the third NMOS transistor, and a source of the fourth NMOS transistor are grounded; and
wherein the PTAT current generation unit comprises a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a third resistor, a fourth resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth resistor, a first bipolar transistor, and a second bipolar transistor, wherein a gate of the fifth PMOS transistor is connected to the external enable signal; a drain of the fifth PMOS transistor, a gate of the sixth PMOS transistor, a gate of the seventh PMOS transistor, the gate of the second PMOS transistor, a drain of the ninth PMOS transistor, one end of the third resistor, and the output unit are connected to each other; a drain of the sixth PMOS transistor is connected to a source of the eighth PMOS transistor; a drain of the seventh PMOS transistor is connected to a source of the ninth PMOS transistor; a gate of the eighth PMOS transistor, a gate of the ninth PMOS transistor, the drain of the third PMOS transistor, the source of the fourth PMOS transistor, the other end of the third resistor, a drain of the seventh NMOS transistor, and the output unit are connected to each other; a drain of the eighth PMOS transistor is connected to one end of the fourth resistor, a gate of the fifth NMOS transistor, and a gate of the seventh NMOS transistor; the other end of the fourth resistor is connected to a drain of the fifth NMOS transistor, a gate of the sixth NMOS transistor, and a gate of the eighth NMOS transistor; a source of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor; a source of the seventh NMOS transistor is connected to a drain of the eighth NMOS transistor; a source of the sixth NMOS transistor is connected to an emitter of the first bipolar transistor; a source of the eighth NMOS transistor is connected to an emitter of the second bipolar transistor via the fifth resistor; a source of the fifth PMOS transistor, a source of the sixth PMOS transistor, and a source of the seventh PMOS transistor are connected to the power supply voltage; and a base and a collector of the first bipolar transistor and a base and a collector of the second bipolar transistor are all grounded.

2. The LDO circuit having the power supply rejection function according to claim 1 , wherein the output unit comprises a tenth PMOS transistor, an eleventh PMOS transistor, a sixth resistor, a third bipolar transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor, wherein a gate of the tenth PMOS transistor and a gate of the twelfth PMOS transistor are connected to the drain of the ninth PMOS transistor and the intermediate frequency zero adjustment unit, a drain of the tenth PMOS transistor is connected to a source of the eleventh PMOS transistor, a drain of the twelfth PMOS transistor is connected to a source of the thirteenth PMOS transistor, a gate of the eleventh PMOS transistor and a gate of the thirteenth PMOS transistor are connected to the other end of the third resistor and the intermediate frequency zero adjustment unit, a drain of the eleventh PMOS transistor and one end of the sixth resistor are connected to the amplifier module, the other end of the sixth resistor is connected to an emitter of the third bipolar transistor, a drain of the thirteenth PMOS transistor is connected to the amplifier module, a source of the tenth PMOS transistor and a source of the twelfth PMOS transistor are connected to the power supply voltage, and a base and a collector of the third bipolar transistor are grounded.

3. The LDO circuit having the power supply rejection function according to claim 2 , wherein the intermediate frequency zero adjustment unit comprises a first capacitor and a second capacitor; one end of the first capacitor and one end of the second capacitor are connected to the power supply voltage; the other end of the first capacitor is connected to the gate of the sixth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the tenth PMOS transistor, and the gate of the twelfth PMOS transistor; and the other end of the second capacitor is connected to the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the thirteenth PMOS transistor.

4. The LDO circuit having the power supply rejection function according to claim 1 , wherein the amplifier module comprises a first-stage amplifier unit, a second-stage amplifier unit, and the intermediate frequency zero generation unit, and
wherein the intermediate frequency zero generation unit is configured between the first-stage amplifier unit and the sec

Assignees

• Vanchip Tianjin Tech Co Ltd

Inventors

• Gao Chenyang
• Lin Sheng

Classifications

• G05F3/30

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/567 Primary

  for temperature compensation · CPC title