Method and device for generating an adjustable bandgap reference voltage

Patent metadata

Field	Value
Publication number	US-9804631-B2
Application number	US-201615243556-A
Country	US
Kind code	B2
Filing date	Aug 22, 2016
Priority date	May 17, 2011
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A circuit includes a first PMOS transistor that includes a first PMOS source coupled to a first input node, a first PMOS gate, and a first PMOS drain. A second PMOS transistor includes a second PMOS source coupled to a second input node, a second PMOS gate, and a second PMOS drain coupled to the second PMOS gate. A first resistor coupled between the first PMOS source and a ground node. A first diode element coupled between the first resistor and the ground node and a second diode element coupled between the second PMOS source and the ground node. A third PMOS transistor includes a third PMOS gate, a third PMOS source coupled to a supply node, and a third PMOS drain coupled to the first input node. A fourth PMOS transistor includes a fourth PMOS gate coupled to the third PMOS gate, a fourth PMOS source coupled to the supply node, and a fourth PMOS drain coupled to the second input node.

First claim

What is claimed is:

1. A circuit comprising:
a first PMOS transistor comprising
a first PMOS source coupled to a first input node,
a first PMOS gate, and
a first PMOS drain;

a second PMOS transistor comprising
a second PMOS source coupled to a second input node,
a second PMOS gate, and
a second PMOS drain coupled to the second PMOS gate;

a first resistor coupled between the first PMOS source and a ground node;
a first diode element coupled between the first resistor and the ground node;
a second diode element coupled between the second PMOS source and the ground node;
a third PMOS transistor comprising
a third PMOS gate,
a third PMOS source coupled to a supply node, and
a third PMOS drain coupled to the first input node;

a fourth PMOS transistor comprising
a fourth PMOS gate coupled to the third PMOS gate,
a fourth PMOS source coupled to the supply node, and
a fourth PMOS drain coupled to the second input node;

a first NMOS transistor coupled between the first PMOS transistor and the ground node, the first NMOS transistor comprising a first NMOS gate;
a second NMOS transistor coupled between the second PMOS transistor and the ground node, the second NMOS transistor comprising a second NMOS gate coupled to the first NMOS gate;
an eleventh PMOS transistor comprising,
an eleventh PMOS gate coupled to the first PMOS gate,
an eleventh PMOS source coupled to the second input node, and
an eleventh PMOS drain:

a fifth NMOS transistor comprising
a fifth NMOS gate coupled to the eleventh PMOS drain,
a fifth NMOS source coupled to the ground node, and
a fifth NMOS drain; and

a twelfth PMOS transistor comprising
a twelfth PMOS source coupled to the supply node,
a twelfth PMOS gate, and
a twelfth PMOS drain coupled to the fifth NMOS drain.

2. The circuit of claim 1 , wherein
the first diode element comprises a first bipolar junction transistor (BJT) connected in diode fashion; and
the second diode element comprises a second BJT connected in diode fashion.

3. The circuit of claim 2 , wherein the first BJT has a first width, and the second BJT has a second width, the first width being different than the second width.

4. The circuit of claim 1 , further comprising:
an eighteenth PMOS transistor comprising
an eighteenth PMOS gate coupled to the twelfth PMOS gate,
an eighteenth PMOS source coupled to the supply node, and
an eighteenth PMOS drain; and

a twelfth NMOS transistor coupled between the eighteenth PMOS transistor and the ground node.

5. The circuit of claim 4 , further comprising:
a thirteenth PMOS transistor comprising
a thirteenth PMOS source coupled to the first input node,
a thirteenth PMOS gate, and
a thirteenth PMOS drain coupled to the thirteenth PMOS gate;

a sixth NMOS transistor comprising
a sixth NMOS source coupled to the ground node,
a sixth NMOS gate coupled to the first NMOS gate, and
a sixth NMOS drain coupled to the thirteenth PMOS drain; and

a seventh NMOS transistor comprising
a seventh NMOS source coupled to the ground node,
a seventh NMOS gate, and
a seventh NMOS drain coupled to the eleventh PMOS drain.

6. The circuit of claim 1 , further comprising:
a fifth PMOS transistor comprising
a fifth PMOS gate coupled to the second PMOS gate,
a fifth PMOS source, and
a fifth PMOS drain; and

a second resistor coupled between the fifth PMOS source and the ground node.

7. The circuit of claim 6 , further comprising:
a fourteenth PMOS transistor comprising
a fourteenth PMOS source coupled to the first input node,
a fourteenth PMOS gate coupled to the second PMOS gate, and
a fourteenth PMOS drain; and

an eighth NMOS transistor comprising
an eighth NMOS source coupled to the ground node,
an eighth NMOS gate, and
an eighth NMOS drain coupled to the fourteenth PMOS drain.

8. The circuit of claim 6 , further comprising:
a sixth PMOS transistor comprising
a sixth PMOS gate,
a sixth PMOS source coupled to the supply node, and
a sixth PMOS drain coupled to the second resistor; and

a third NMOS transistor coupled between the fifth PMOS drain and the ground node.

9. The circuit of claim 8 , further comprising:
a fifteenth PMOS transistor comprising
a fifteenth PMOS source coupled to the sixth PMOS drain,
a fifteenth PMOS gate, and
a fifteenth PMOS drain coupled to the ground node;

a ninth NMOS transistor coupled between the fifteenth PMOS transistor and the ground node; and
a sixteenth PMOS transistor comprising
a sixteenth PMOS gate coupled to the fifteenth PMOS gate,
a sixteenth PMOS source coupled to the second input node, and
a sixteenth PMOS drain coupled to the ground node.

10. The circuit of claim 9 , further comprising:
a tenth NMOS transistor coupled between the sixteenth PMOS transistor and the ground node;
an eleventh NMOS transistor coupled to the tenth NMOS transistor; and
a seventeenth PMOS transistor coupled between the supply node and the eleventh NMOS transistor.

11. The circuit of claim 8 , further comprising:
a seventh PMOS transistor comprising
a seventh PMOS gate coupled to the sixth PMOS gate,
a seventh PMOS source coupled to the supply node, and
a seventh PMOS drain;

a fourth NMOS transistor coupled between the seventh PMOS transistor and the ground node; and
an eighth PMOS transistor comprising
an eighth PMOS source coupled to the seventh PMOS drain,
an eighth PMOS gate, and
an eighth PMOS drain coupled to the fourth NMOS transistor.

12. The circuit of claim 11 , further comprising:
a ninth PMOS transistor comprising
a ninth PMOS source coupled to the supply node,
a ninth PMOS gate coupled to the fourth PMOS gate, and
a ninth PMOS drain;

a third resistor coupled between the ninth PMOS transistor and the ground node; and
a tenth PMOS transistor comprising
a tenth PMOS gate,
a tenth PMOS source coupled to the ninth PMOS drain, and
a tenth PMOS drain coupled to the third resistor.

13. The circuit of claim 12 , wherein the tenth PMOS gate is coupled to the eighth PMOS gate.

14. A circuit comprising:
a first transistor comprising
a first source coupled to a first input node,
a first gate, and
a first drain;

a second transistor comprising
a second source coupled to a second input node,
a second gate, and
a second drain coupled to the second gate;

a first resistor coupled between the first source and a second supply node;
a first BJT coupled between the first resistor and the second supply node;
a second BJT coupled between the second source and the second supply node;
a third transistor comprising
a third gate,
a third source coupled to a first supply node, and
a third drain coupled to the first input node; and

a fourth transistor comprising
a fourth gate coupled to the third gate;
a fourth source coupled to the first supply node;
a fourth drain coupled to the second input node;

a fifth transistor coupled between the first transistor and the second supply node, the fifth transistor comprising a fifth gate; and
a sixth transistor coupled between the second transistor and the second supply node, the sixth transistor comprising a sixth gate coupled to the fifth gate;
a seventh transistor comprising
a seventh gate coupled to the second gate,
a seventh source, and
a seventh drain;

a second resistor coupled between the seventh source and the second supply node;
an eighth transistor comprising
an eighth source coupled to the first input node,
an eighth gate coupled to the second gate, and
an eighth drain; and

a ninth transistor comprising
a ninth source coupled to the seco

Assignees

• Stmicroelectronics Rousset

Inventors

• Fort Jimmy
• Soude Thierry

Classifications

• G05F3/267 Primary

  using both bipolar and field-effect technology · CPC title

• G05F3/30

  Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) · CPC title

• G05F1/468

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title