Deep trench isolation structure and methods for fabrication thereof

Patent metadata

Field	Value
Publication number	US-12408448-B2
Application number	US-202217838994-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jun 13, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

First claim

The invention claimed is:

1. A method comprising:
forming a plurality of pixel elements in and on a front side of a semiconductor substrate;
forming deep isolation trenches from a backside of the semiconductor substrate, wherein the deep isolation trenches surround a plurality of doped regions corresponding to the plurality of pixel elements;
depositing a defect repairing layer on sidewalls of the deep isolation trenches, wherein the defect repairing layer comprises a metal hydroxide;
depositing a hole accumulation layer on the defect repairing layer, wherein the hole accumulation layer comprises a metal oxide;
over-oxidizing the hole accumulation layer to add interstitial oxygen to the hole accumulation layer;
filling the deep isolation trenches with a filling material;
forming a plurality of color filters; and
forming a plurality of micro lenses.

2. The method of claim 1 , wherein the defect repairing layer comprises aluminum hydroxide (AlOH).

3. The method of claim 2 , wherein the defect repairing layer has a thickness in a range between about 1 angstrom and about 50 nm.

4. The method of claim 1 , wherein depositing the hole accumulation layer comprises depositing a high-k dielectric layer.

5. The method of claim 4 , wherein over-oxidizing the hole accumulation layer comprises treating the hole accumulation layer with a plasma of oxygen source at a temperature below about 410° C.

6. The method of claim 5 , wherein a ratio of interstitial oxygen over bulk oxygen in the hole accumulation layer is greater than 7%.

7. The method of claim 5 , wherein the hole accumulation layer has a thickness in a range between about 50 angstroms and 500 angstroms.

8. The method of claim 1 , wherein a density of defect traps at an interface between the defect repairing layer and the semiconductor substrate in a range between 3.6E11 and about 4.2E11.

9. A method, comprising:
doping a semiconductor substrate to form a doped region with a first dopant;
doping a gap region around the doped region with a second dopant;
forming a pixel element over the doped region and the gap region from a front surface of the semiconductor substrate;
forming an interconnect structure over the pixel element;
etching a deep isolation trench in the gap region from a back surface of the semiconductor substrate;
passivating dangling semiconductor bonds on sidewalls of the deep isolation trench by depositing a defect repairing layer on the sidewalls of the deep isolation trench;
depositing a high-k dielectric layer on the defect repairing layer;
treating the high-k dielectric layer with an oxygen source to increase interstitial oxygen in the high-k dielectric layer;
depositing a filling material on the high-k dielectric layer to fill the deep isolation trench;
performing a planarization process to remove the filing material, the high-k dielectric layer and the defect repairing layer from the back surface of the substrate;
forming a color filter on the back surface of the semiconductor substrate; and
forming a micro lens on the color filter.

10. The method of claim 9 , wherein a ratio of interstitial oxygen over bulk oxygen in the high-k dielectric layer is in a range between 7% and 12%.

11. The method of claim 10 , wherein a density of defect traps on an interface between the defect repairing layer and the gap region of the semiconductor substrate in a range between 3.6E11 and about 4.2E11.

12. A structure, comprising:
a plurality of pixel elements formed in and on a semiconductor substrate;
a deep trench isolation (DTI) structure formed in the semiconductor substrate, wherein the DTI structure separates individual pixel elements, and the DTI structure comprises:
a defect repairing layer in contact with the semiconductor substrate, wherein the defect repairing layer contains hydrogen, and the defect repairing layer contains a metal hydroxide;
a hole accumulation layer in contact with the defect repairing layer, wherein the hole accumulation layer comprises a high-k dielectric material having an areal oxygen density greater than an areal oxygen density of silicon oxide, and
a filling material in contact with the hole accumulation layer.

13. The structure of claim 12 , wherein the hole accumulation layer comprises a metal oxide, and a ratio of interstitial oxygen over bulk oxygen is greater than 7%.

14. The structure of claim 13 , wherein the ratio of interstitial oxygen over bulk oxygen in the hole accumulation layer is less than 12%.

15. The structure of claim 12 , wherein the defect repairing layer comprises one of aluminum hydroxide (AlOH).

16. The structure of claim 15 , wherein the defect repairing layer has a thickness in a range between about 1 angstrom and about 50 nm.

17. The structure of claim 12 , wherein the deep trench isolation structure is formed in a back surface of the semiconductor substrate, and an absorption enhancement layer is formed on the back surface of the semiconductor substrate and the deep trench isolation structure.

18. The structure of claim 12 , wherein the defect repairing layer has a first thickness, the hole accumulation layer has a second thickness, a ratio of the first thickness over the second thickness is in a range between about 0.01 and about 1.0.

19. The method of claim 9 , wherein depositing the defect repairing layer comprises performing a low temperature deposition at a temperature lower than about 400° C.

20. The method of claim 9 , wherein treating the high-k dielectric layer comprises treating the high-k dielectric layer with a plasma of oxygen source at a temperature range between about 300° C. and about 400° C.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Bi-Shen
• Hu Chia-Wei
• Trinh Hai-Dang
• Tsai Min-Ying
• Li Ching I
• Kuang Hsun-Chung
• Tsai Cheng-Yuan

Classifications

• H10F39/8063

  Microlenses · CPC title

• H10F39/8053

  Colour filters · CPC title

• H10F39/807 Primary

  Pixel isolation structures · CPC title

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/182

  Colour image sensors · CPC title