Method of making amphi-FET structure and method of designing

Patent metadata

Field	Value
Publication number	US-12408440-B2
Application number	US-202418734212-A
Country	US
Kind code	B2
Filing date	Jun 5, 2024
Priority date	Mar 26, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A semiconductor device includes a substrate. The semiconductor device further includes a first gate structure on a first side of the substrate. The semiconductor device further includes a second gate structure on a second side of the substrate, wherein the first side is opposite the second side. The semiconductor device further includes a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first gate structure on a first side of the substrate;
a second gate structure on a second side of the substrate, wherein the first side is opposite the second side; and
a gate via extending through the substrate, wherein the gate via directly connects to the first gate structure, and the gate via directly connects to the second gate structure.

2. The semiconductor device of claim 1 , wherein the first gate structure is configured to control conductivity of a portion of a first active region, and the second gate structure is configured to control conductivity of a portion of a second active region.

3. The semiconductor device of claim 2 , wherein the gate via is offset from the first active region in a direction parallel to a top surface of the substrate in a cross-sectional view.

4. The semiconductor device of claim 2 , further comprising:
a first source/drain (S/D) electrode electrically connected to the first active region; and
a second S/D electrode electrically connected to the second active region.

5. The semiconductor device of claim 4 , further comprising a S/D via electrically connecting the first S/D electrode to the second S/D electrode, wherein the S/D via extends through the substrate.

6. The semiconductor device of claim 5 , wherein a width of the S/D via measured in a first direction parallel to a top surface of the substrate is equal to a width of the second S/D electrode.

7. The semiconductor device of claim 6 , wherein the first S/D electrode extends beyond the second S/D electrode in the first direction.

8. The semiconductor device of claim 6 , wherein the width of the S/D via is equal to a width of the first S/D electrode.

9. The semiconductor device of claim 1 , further comprising a first power rail on the first side of the substrate, wherein the first power rail is electrically connected to the first gate structure.

10. The semiconductor device of claim 9 , further comprising a second power rail on the second side of the substrate, wherein the second power rail is electrically connected to the second gate structure.

11. A method of making a semiconductor device, the method comprising:
forming a first source/drain (S/D) electrode on a first side of a substrate;
forming an S/D connect via extending through the substrate; and
forming a second S/D electrode on a second side of the substrate, wherein the first side is opposite the second side, and the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.

12. The method of claim 11 , further comprising forming a first gate structure on the first side of the substrate, wherein the first gate structure is configured to control conductivity of a first active region electrically connected to the first S/D electrode.

13. The method of claim 12 , further comprising forming a second gate structure on the second side of the substrate, wherein the second gate structure is configured to control conductivity of a second active region electrically connected to the second S/D electrode.

14. The method of claim 13 , further comprising forming a gate via extending through the substrate, wherein the gate via electrically connects the first gate structure to the second gate structure.

15. The method of claim 14 , wherein forming the gate via comprises forming the gate via in direct contact with the first gate structure and in direct contact with the second gate structure.

16. The method of claim 11 , wherein forming the second S/D electrode comprises forming the second S/D electrode having a same width as the S/D connect via.

17. The method of claim 11 , wherein forming the second S/D electrode comprises forming the second S/D electrode having a different width from the first S/D electrode.

18. A semiconductor device comprising:
a substrate;
a first active region on a first side of the substrate;
a second active region on a second side of the substrate opposite the first side;
a first electrode surrounding a portion of the first active region;
a second electrode surrounding a portion of the second active region; and
a via extending through the substrate, wherein the via directly connects to the first electrode, and the via directly connects to the second electrode.

19. The semiconductor device of claim 18 , wherein the first electrode is a gate electrode.

20. The semiconductor device of claim 18 , wherein the first electrode is a source/drain (S/D) electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chih-Yu
• Chen Chih-Liang
• Lu Chi-Yu
• Ciou Shang-Syuan
• Zhuang hui-zhong
• Tsai Ching-Wei
• Chang Shang-Wen

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title