Semiconductor memory device having a confinement layer with a two-dimensional electron gas in the confinement layer

Patent metadata

Field	Value
Publication number	US-12408382-B2
Application number	US-202217694903-A
Country	US
Kind code	B2
Filing date	Mar 15, 2022
Priority date	May 14, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a bit line extending in a first direction;
a channel pattern on the bit line, the channel pattern including a first oxide semiconductor layer contacting the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, each of the first and second oxide semiconductor layers including a horizontal part parallel to the bit line and a first vertical part and a second vertical part that vertically protrude from the horizontal part;
a first word line and a second word line that are between the first and second vertical parts of the second oxide semiconductor layer and are on the horizontal part of the second oxide semiconductor layer, the first and second word lines running across the bit line; and
a gate dielectric pattern between the channel pattern and the first and second word lines, the gate dielectric pattern on the first and second vertical parts,
wherein a thickness of the second oxide semiconductor layer is greater than a thickness of the first oxide semiconductor layer.

2. The semiconductor memory device of claim 1 ,
wherein a concentration of gallium (Ga) of the channel pattern increases with distance from the first word line.

3. The semiconductor memory device of claim 1 , wherein each of the first and second oxide semiconductor layers includes indium gallium zinc oxide (IGZO), and
wherein a concentration of gallium (Ga) in the first oxide semiconductor layer is greater than a concentration of gallium (Ga) in the second oxide semiconductor layer.

4. The semiconductor memory device of claim 1 , wherein a band gap of the first oxide semiconductor layer is greater than a band gap of the second oxide semiconductor layer.

5. The semiconductor memory device of claim 1 , wherein a work function of the first oxide semiconductor layer is less than a work function of the second oxide semiconductor layer.

6. The semiconductor memory device of claim 1 , wherein top surfaces of either the first and second word lines are at a level lower than a lowest level of top surfaces of either the first and second vertical parts of the second oxide semiconductor layer.

7. The semiconductor memory device of claim 1 , wherein a thickness of the channel pattern is in a range of about 4 nm to about 10 nm.

8. The semiconductor memory device of claim 7 , wherein
the thickness of the first oxide semiconductor layer is in a range of about 1 nm to about 3 nm, and
the thickness of the second oxide semiconductor layer is in a range of about 3 nm to about 7 nm.

9. The semiconductor memory device of claim 1 , wherein the channel pattern includes a horizontal part parallel to the bit line, and a first vertical part and a second vertical part that vertically protrude from the horizontal part of the channel pattern,
the horizontal part of the channel pattern includes the horizontal part of the first oxide semiconductor layer and the horizontal part of the second oxide semiconductor layer,
the first vertical part of the channel pattern includes the first vertical part of the first oxide semiconductor layer and the first vertical part of the second oxide semiconductor layer, and
the second vertical part of the channel pattern includes the second vertical part of the first oxide semiconductor layer and the second vertical part of the second oxide semiconductor layer.

10. The semiconductor memory device of claim 9 , wherein
the first vertical part of the channel pattern connects to a first data storage pattern, and
the second vertical part of the channel pattern connects to a second data storage pattern.

11. A semiconductor memory device, comprising:
a bit line extending in a first direction;
a channel pattern on the bit line, the channel pattern including a horizontal part parallel to the bit line, and a first vertical part and a second vertical part that vertically protrude from the horizontal part;
a first word line on the horizontal part of the channel pattern, the first word line running across the bit line and extending in a second direction; and
a gate dielectric pattern between the first word line and the channel pattern, the gate dielectric pattern on the first vertical part,
wherein the channel pattern includes,
a first oxide semiconductor layer in contact with the bit line, and
a second oxide semiconductor layer on the first oxide semiconductor layer,

wherein a concentration of gallium (Ga) in the first oxide semiconductor layer is greater than a concentration of gallium (Ga) in the second oxide semiconductor layer.

12. The semiconductor memory device of claim 11 ,
wherein a concentration of gallium (Ga) of the channel pattern increases with distance from the first word line.

13. The semiconductor memory device of claim 11 , further comprising:
a data storage pattern connected in common to the first and second vertical parts of the channel pattern.

14. The semiconductor memory device of claim 13 , further comprising:
a second word line on the horizontal part of the channel pattern and apart from the first word line, the second word line extending in the second direction,
wherein each of the first and second vertical parts of the channel pattern has an inner sidewall and an outer sidewall that are opposite to each other, the inner sidewalls of the first and second vertical parts facing each other,
the first word line includes a first inner gate electrode adjacent to the inner sidewall of the first vertical part and includes a first outer gate electrode adjacent to the outer sidewall of the first vertical part, and
the second word line includes a second inner gate electrode adjacent to the inner sidewall of the second vertical part and includes a second outer gate electrode adjacent to the outer sidewall of the second vertical part.

15. The semiconductor memory device of claim 11 , further comprising:
a second word line on the horizontal part of the channel pattern and spaced apart from the first word line, the second word line extending in the second direction,
wherein an outer sidewall of the first word line is adjacent to the first vertical part, and
an outer sidewall of the second word line is adjacent to the second vertical part.

16. The semiconductor memory device of claim 1 , wherein the second oxide semiconductor layer is directly on the first oxide semiconductor layer.

17. The semiconductor memory device of claim 1 , wherein the second oxide semiconductor layer and the first oxide semiconductor layer have an interface therebetween.

18. The semiconductor memory device of claim 17 , wherein the first oxide semiconductor layer and the second oxide semiconductor layer are configured to have a two-dimensional electron gas formed at the interface.

19. The semiconductor memory device of claim 11 , wherein the second oxide semiconductor layer and the first oxide semiconductor layer have an interface therebetween.

20. The semiconductor memory device of claim 11 ,
wherein the second oxide semiconductor layer is directly on the first oxide semiconductor layer.

Assignees

• Samsung Electronics Co Ltd
• Iucf Hyu

Inventors

• Jeong Jae Kyeong
• Ryu Min Tae
• Seul Hyeon Joo
• Yoo Sungwon
• Lee Wonsok
• Cho Min Hee
• Hur Jae Seok

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/478

  the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body · CPC title