Memory arrays, and methods of forming memory arrays

Patent metadata

Field	Value
Publication number	US-12408341-B2
Application number	US-202217692004-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Dec 27, 2017
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

First claim

We claim:

1. An assembly, comprising:
a channel region including a first channel portion and a second channel portion under the first channel portion;
a tunneling material extending along an entirety of the channel region;
a first memory cell structure located between a first gate and the first channel portion; the first memory cell structure including a first charge-storage region and a first charge-blocking region; the first charge-blocking region being located between the first charge-storage region and the first gate;
a second memory cell structure under the first memory cell structure and located between a second gate and the second channel portion; the second memory cell structure including a second charge-storage region and a second charge-blocking region; the second charge-blocking region being located between the second charge-storage region and the second gate;
a void between the first and second gates, and between the first and second memory cell structures and extending to the tunneling material;
a first liner between the silicon nitride of the first charge-storage region and the void;
a second liner between the silicon nitride of the second charge-storage region and the void;
a first dielectric barrier region being between the first gate and the first charge-blocking region, the first dielectric barrier region being directly against the void along a lower surface of the first charge-blocking region;
a second dielectric barrier region being between the second gate and the second charge-blocking region, the second dielectric barrier region being directly against the void along an upper surface of the second charge-blocking region;
a first region of a low-density silicon dioxide between the first gate and the void;
a second region of the low-density silicon dioxide between the second gate and the void;
an insulative material along and directly contacting a portion of the first region of low-density silicon dioxide and along and directly contacting a portion of the second regions of low-density silicon dioxide, the insulative material comprising silicon dioxide having a higher density than the low-density silicon dioxide of the first and second regions; and
wherein an edge of the first dielectric barrier region is directly against the void; and wherein an edge of the second dielectric barrier region is directly against the void, and wherein the first region of low-density silicon dioxide does not contact the second region of low-density silicon dioxide.

2. The assembly of claim 1 wherein the first and second liners comprise silicon oxynitride.

3. The assembly of claim 1 wherein the first and second charge-blocking regions comprise silicon oxynitride and the first and second charge-storage regions comprise silicon nitride.

4. The assembly of claim 3 wherein the first charge-blocking region comprises silicon dioxide between the silicon oxynitride of the first charge-blocking region and the silicon nitride of the first charge-storage region; and wherein the second charge-blocking region comprises silicon dioxide between the silicon oxynitride of the second charge-blocking region and the silicon nitride of the second charge-storage region.

5. A method of forming an assembly, comprising:
forming a channel region having a first channel portion and a second channel portion under the first channel portion;
forming a first memory cell structure located between a first gate and the first channel portion; the first memory cell structure including a first charge-storage region and a first charge-blocking region; the first charge-blocking region being located between the first charge-storage region and the first gate;
forming a second memory cell structure under the first memory cell structure and located between a second gate and the second channel portion;
the second memory cell structure including a second charge-storage region and a second charge-blocking region; the second charge-blocking region being located between the second charge-storage region and the second gate;
forming a void between the first and second gates, and between the first and second memory cell structures;
forming a first liner between the silicon nitride of the first charge-storage region and the void;
forming a second liner between the silicon nitride of the second charge-storage region and the void;
forming a high-k dielectric barrier material between the first gate and the first charge-blocking region, the first high-k dielectric barrier material being directly against the void along a lower surface of the first charge-blocking region;
forming the high-k dielectric barrier material between the second gate and the second charge-blocking region, the high-k dielectric barrier material being directly against the void along an upper surface of the second charge-blocking region;
forming a first region of a low-density silicon dioxide between the first gate and the void;
forming a second region of the low-density silicon dioxide between the second gate and the void; wherein the first region of low-density silicon dioxide does not contact the second region of low-density silicon dioxide; and
forming an insulative material along and directly contacting a portion of the first region of low-density silicon dioxide and along and directly contacting a portion of the second regions of low-density silicon dioxide, the insulative material comprising silicon dioxide having a higher density than the low-density silicon dioxide of the first and second regions.

6. The method of claim 5 wherein the first and second liners comprise silicon oxynitride.

7. The method of claim 5 wherein the first and second charge-blocking regions comprise silicon oxynitride and the first and second charge-storage regions comprise silicon nitride.

8. The method of claim 7 wherein the first charge-blocking region comprises silicon dioxide between the silicon oxynitride of the first charge-blocking region and the silicon nitride of the first charge-storage region; and wherein the second charge-blocking region comprises silicon dioxide between the silicon oxynitride of the second charge-blocking region and the silicon nitride of the second charge-storage region.

Assignees

• Micron Technology Inc

Inventors

• Kim Changhan
• Carter Chet E
• Smith Cole
• Howder Collin
• Hill Richard J
• Li Jie

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title