Digital-to-analog converter and a method for reducing aging effects on components of the digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-12407354-B2
Application number	US-202117645462-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) comprising:
a plurality of DAC cells; and
a controller configured to generate a control signal to drive the plurality of DAC cells for each clock cycle, wherein the controller is configured to generate the control signal to select a set of at least one DAC cell for an input code or for a standby mode of the DAC such that the selected set of at least one DAC cell to be active for the same input code or for the standby mode of the DAC change during a predetermined period of time, wherein an output of the DAC is less than or equal to a predefined threshold,
wherein during a normal operation of the DAC where the DAC generates the output based on the input code, the controller is configured to generate the control signal in a way that one or more low-indexed DAC cells are swapped with one or more high-indexed DAC cells such that the selected set of at least one DAC cell to be active for the same input code changes during the predetermined period of time.

2. The DAC of claim 1 , further comprising at least one redundant DAC cell, wherein the controller is configured to generate the control signal to select the set of at least one DAC cell to be active for the input code or for the standby mode of the DAC including the at least one redundant DAC cell.

3. The DAC of claim 2 , wherein the DAC cells are either binary-weighted or unary-weighted.

4. The DAC of claim 1 , wherein, in the standby mode, the controller is configured to generate the control signal in a way that the set of at least one DAC cell selected for a predetermined level of the output of the DAC changes during the predetermined period of time.

5. The DAC of claim 4 , wherein the controller is configured to generate the control signal in a way that the set of at least one DAC cell selected among the plurality of DAC cells is cyclically shifted by a predetermined number of DAC cells periodically.

6. The DAC of claim 5 , wherein the controller is configured to generate the control signal in a way that the set of at least one DAC cell selected among the plurality of DAC cells is cyclically shifted by a random number of DAC cells periodically.

7. The DAC of claim 4 , wherein during the standby mode, the controller is configured to alternatingly select the set of at least one DAC cell starting from a lowest-indexed DAC cell for one period of time and starting from a highest-indexed DAC cell for a subsequent period of time or change DAC cell indexing such that the set of at least one DAC cell selected for a predetermined level of the output of the DAC changes during the predetermined period of time.

8. The DAC of claim 1 , wherein in case two or more low-indexed DAC cells are swapped with two or more high-indexed DAC cells, the two or more low-indexed DAC cells and the two or more high-indexed DAC cells are swapped at the same time.

9. The DAC of claim 1 , wherein in case two or more low-indexed DAC cells are swapped with two or more high-indexed DAC cells, each of the two or more low-indexed DAC cells and each of the two or more high-indexed DAC cells are swapped at different times.

10. The DAC of claim 1 , wherein the controller is configured to generate the control signal based on signal statistics and properties of an input signal.

11. The DAC of claim 1 , wherein the controller is configured to alternatingly select the set of at least one DAC cell starting from a lowest-indexed DAC cell for one period of time and starting from a highest-indexed DAC cell for a subsequent period of time.

12. The DAC of claim 1 , wherein the plurality of DAC cells are segmented into two or more segments, and DAC cells in at least one segment is unary coded.

13. The DAC of claim 1 , wherein the driver is an inverter-based driver.

14. A method for reducing aging effects on components of a digital-to-analog converter (DAC), wherein the DAC comprises a plurality of DAC cells, the method comprising:
generating a control signal for driving the plurality of DAC cells for each clock cycle, wherein the control signal is generated to select a set of at least one DAC cell for an input code or for a standby mode of the DAC such that the selected set of at least one DAC cell to be active for the same input code or for the standby mode of the DAC change during a predetermined period of time, wherein an output of the DAC is less than or equal to a predefined threshold; and
sending the control signal to the DAC cells,
wherein during a normal operation of the DAC where the DAC generates the output based on the input code, the control signal is generated in a way that one or more low-indexed DAC cells are swapped with one or more high-indexed DAC cells such that the selected set of at least one DAC cell to be active for the same input code changes during the predetermined period of time.

15. The method of claim 14 , wherein the DAC comprises at least one redundant DAC cell, wherein the control signal is generated to select the set of at least one DAC cell to be active for the input code or for the standby mode of the DAC including the at least one redundant DAC cell.

16. The method of claim 14 , wherein the DAC cells are either binary-weighted or unary-weighted.

17. The method of claim 14 , wherein, in the standby mode, the control signal is generated in a way that the set of at least one DAC cell selected for a predetermined level of the output of the DAC changes during the predetermined period of time.

18. The method of claim 17 , wherein the control signal is generated in a way that the set of at least one DAC cell selected among the plurality of DAC cells is cyclically shifted by a predetermined number of DAC cells or a random number of DAC cells periodically.

19. The method of claim 14 , wherein the control signal is generated in a way that the set of at least one DAC cell is alternatingly selected starting from a lowest-indexed DAC cell for one period of time and starting from a highest-indexed DAC cell for a subsequent period of time.

Assignees

• Intel Corp

Inventors

• Gruber Daniel
• Kalcher Michael
• Cangianiello Alessandra

Classifications

• H03M1/0682

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title