Techniques for processing devices

Patent metadata

Field	Value
Publication number	US-12406975-B2
Application number	US-202318541869-A
Country	US
Kind code	B2
Filing date	Dec 15, 2023
Priority date	Feb 15, 2018
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

First claim

What is claimed is:

1. A bonded structure comprising:
a substrate directly hybrid bonded to a die along a bonding interface without an intervening adhesive, the die having a smaller footprint than a footprint of the substrate,
wherein the substrate comprises one or more metal features, wherein the die comprises one or more metal features, and wherein the one or more metal features of the substrate are directly bonded to the one more metal features of the die at the bond interface,
wherein one of the die and the substrate comprises a characteristic profile of having been activated with an activating species prior to bonding, and the other of the die and the substrate lacks the characteristic profile of having been activated with the activating species prior to bonding.

2. The bonded structure of claim 1 , wherein the activating species comprises nitrogen.

3. The bonded structure of claim 1 , wherein the substrate is directly bonded to the die with a hybrid bond having a bond energy of at least 1000 mJ/m 2 .

4. The bonded structure of claim 1 , wherein the substrate comprises a first insulating region that at least partially surrounds the one or more metal features of the substrate, wherein the die comprises a second insulating region that at least partially surrounds the one ore more metal features of the die, and wherein the first insulating region is directly bonded to the second insulating region without an adhesive.

5. The bonded structure of claim 4 , wherein the first insulating region is directly bonded to the second insulating region with a chemical bond.

6. A method of forming a microelectronic assembly, the method comprising:
providing a substrate having a first bonding surface, wherein the first bonding surface comprises a first metal feature;
providing a die having a second bonding surface, wherein the second bonding surface comprises a second metal feature;
plasma activating only one of the first bonding surface and the second bonding surface; and
hybrid bonding the second bonding surface to the first bonding surface without an adhesive and without activating the other of the first bonding surface and the second bonding surface, wherein, after hybrid bonding the second bonding surface to the first bonding surface, the first and second metal features are directly bonded together.

7. The method of claim 6 , wherein plasma activating only one of the first bonding surface and the second bonding surface comprises activating only one of the first and bonding surface and the second bonding surface with a nitrogen plasma.

8. The method of claim 6 , further comprising:
before plasma activating only one of the first bonding surface and the second bonding surface, cleaning the only one of the first bonding surface and the second bonding surface.

9. The method of claim 8 , wherein cleaning the only one of the first bonding surface and the second bonding surface comprises plasma cleaning the only one of the first bonding surface and the second bonding surface.

10. The method of claim 9 , wherein plasma cleaning the only one of the first bonding surface and the second bonding surface comprises cleaning the only one of the first bonding surface and the second bonding surface with oxygen plasma.

11. The method of claim 9 , wherein plasma cleaning the only one of the first bonding surface and the second bonding surface comprises exposing the second bonding surface to oxygen plasma without exposing the first bonding surface to oxygen plasma.

12. The method of claim 6 , wherein:
the first bonding surface comprises a first conductive feature and a first insulating region at least partially surrounding the first conductive feature,
the second bonding surface comprises a second conductive feature and a second insulating region at least partially surrounding the second conductive feature, and
hybrid bonding the first bonding surface to the second bonding surface comprises directly hybrid bonding the first bonding surface to the second bonding surface such that the first conductive feature is directly bonded to the second conductive feature and the first nonconductive region is directly bonded to the second nonconductive region.

13. The method of claim 6 , wherein hybrid bonding the second bonding surface to the first bonding surface without an adhesive comprises forming a hybrid bond having a bond energy of at least 1000 mJ/m 2 .

14. A method of forming a microelectronic assembly, the method comprising:
preparing a bonding surface of a first substrate;
preparing a bonding surface of a second substrate;
applying a protective coating to the bonding surface of the second substrate;
singulating the second substrate into a plurality of dies, wherein the plurality of dies comprises a first die, wherein the first die has a bonding surface that comprises a portion of the bonding surface of the second substrate and has a portion of the protective coating;
plasma activating the bonding surface of the first substrate;
cleaning off the portion of the protective coating from the first die to expose the bonding surface of the first die; and
directly bonding the bonding surface of the first die to the bonding surface of the first substrate without an adhesive,
wherein the bonding surface of the first die is not activated before it is directly bonded to the bonding surface of the first substrate.

15. The method of claim 14 , wherein plasma activating the bonding surface of the first substrate comprises plasma activating the bonding surface of the first substrate with a first plasma.

16. The method of claim 15 , wherein the first plasma comprises a nitrogen plasma.

17. The method of claim 15 , wherein cleaning off the portion of the protective coating from the first die to expose the bonding surface of the first die comprises cleaning off the portion of the protective coating from the first die with a non-activating second plasma that is different from the first plasma.

18. The method of claim 17 , wherein the second plasma comprises an oxygen plasma.

19. The method of claim 17 , wherein the bonding surface of the first die is not exposed to the second plasma.

20. The method of claim 14 , wherein cleaning off the portion of the protective coating from the first die to expose the bonding surface die comprises cleaning off the portion of the protective coating from the first die with a reactive ion etching process.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Uzoh Cyprian Emeka
• Mirkarimi Laura Wills
• Gao Guilian
• Fountain Jr Gaius Gillman

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title