Memory circuitry and method used in forming memory circuitry

Patent metadata

Field	Value
Publication number	US-12406932-B2
Application number	US-202217881308-A
Country	US
Kind code	B2
Filing date	Aug 4, 2022
Priority date	Aug 4, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A lining is formed in and that less-than-fills the cavity atop treads of the stairs. Individual of the treads comprise conducting material of one of the first tiers in the finished-circuitry construction. The lining that is atop the treads is replaced with at least one of metal material, polysilicon, or SiGe and insulative material is provided in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe. Conductive vias are formed through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe. Individual of the conductive vias are directly above and directly against the conducting material of one of the individual treads. Other embodiments, including structure, are disclosed.

First claim

The invention claimed is:

1. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction;
forming a lining in and that less-than-fills the cavity atop treads of the stairs, individual of the treads comprising conducting material of one of the first tiers in the finished-circuitry construction;
replacing the lining that is atop the treads with at least one of metal material, polysilicon, or SiGe and providing insulative material in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe; and
forming conductive vias through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe; individual of the conductive vias being directly above and directly against the conducting material of one of the individual treads.

2. The method of claim 1 wherein the providing of the insulative material in the remaining volume of the cavity occurs before the replacing of the lining with the at least one of the metal material, the polysilicon, or the SiGe.

3. The method of claim 1 wherein the at least one comprises metal material.

4. The method of claim 1 wherein the at least one comprises polysilicon.

5. The method of claim 1 wherein the at least one comprises SiGe.

6. The method of claim 1 wherein the forming of the conductive vias comprises:
first etching conductive via openings through the insulative material for the conductive vias and using the at least one of the metal material, the polysilicon, or the SiGe as an etch-stop during the first etching such that the conductive via openings stop atop or within the at least one of the metal material, the polysilicon, or the SiGe;
after the first etching, second etching through the at least one of the metal material, the polysilicon, or the SiGe to extend the conductive via openings deeper and exposing the conducting material of the individual treads; and
forming the individual conductive vias in individual of the extended conductive via openings.

7. The method of claim 1 wherein the individual treads in the finished-circuitry construction comprise:
the at least one of the metal material, the polysilicon, or the SiGe;
the conducting material of one of the first tier directly below the at least one of the metal material, the polysilicon, or the SiGe; and
an intervening insulating material vertically-between the at least one of the metal material, the polysilicon, or the SiGe and the conducting material of the one first tier that is directly below the at least one of the metal material, the polysilicon, or the SiGe.

8. The method of claim 7 wherein the at least one of the metal material, the polysilicon, or the SiGe and the conducting material of the one first tier that is directly below the at least one of the metal material, the polysilicon, or the SiGe are of different compositions relative one another.

9. The method of claim 8 wherein the at least one of the metal material, the polysilicon, or the SiGe is conductive.

10. The method of claim 9 wherein the at least one of the metal material, the polysilicon, or the SiGe and the conducting material of the one first tier that is directly below the at least one of the metal material, the polysilicon, or the SiGe are of different compositions relative one another.

11. The method of claim 9 wherein the at least one of the metal material, the polysilicon, or the SiGe and the conducting material of the one first tier that is directly below the at least one of the metal material, the polysilicon, or the SiGe are of the same composition relative one another.

12. The method of claim 7 wherein the at least one of the metal material, the polysilicon, or the SiGe is insulative.

13. The method of claim 12 wherein the at least one of the metal material, the polysilicon, or the SiGe comprises Al 2 O 3 .

14. The method of claim 7 comprising forming a through-array-via (TAV) construction extending through the insulative material, through the at least one of the metal material, the polysilicon, or the SiGe, through the intervening insulating material, and through the conducting material of the one first tier that is directly below the at least one of the metal material, the polysilicon, or the SiGe of the individual treads.

15. The method of claim 14 comprising multiple of the TAV constructions per individual tread.

16. The method of claim 15 wherein the at least one of the metal material, the polysilicon, or the SiGe is conductive and is horizontally-continuous among the multiple TAV constructions in the respective individual tread.

17. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction;
forming a lining in and that less-than-fills the cavity atop treads of the stairs, the treads individually comprising conducting material of one of the first tiers in the finished-circuitry construction;
forming insulative material in remaining volume of the cavity directly above the lining;
forming through-array-via (TAV) openings through the insulative material and the treads, multiple of the TAV openings per tread extending through individual of the treads;
through the TAV openings, isotropically etching the lining laterally-outward relative to the TAV openings to horizontally interconnect the multiple TAV openings into a single opening per tread where the etched lining was;
through the TAV openings, forming at least one of metal material, polysilicon, or SiGe in the single opening where the etched lining was and across horizontal locations where conductive vias to the conducting material of the individual treads will be formed;
first etching conductive via openings through the insulative material in the horizontal locations to and using the at least one of the metal material, the polysilicon, or the SiGe as an etch-stop during the first etching such that the conductive via openings stop atop or within the at least one of the metal material, the polysilicon, or the SiGe;
after the first etching, second etching through the at least one of the metal material, the polysilicon, or the SiGe to extend the conductive via openings deeper and exposing the conducting material of the individual treads; and
forming conductive vias in the extended conductive via openings, individual of the conductive vias being directly above and directly against the conducting material of one of the individual treads.

18. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the first tiers comprising silicon nitride, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction;
forming a lining in and that less-than-fills the cavity atop treads of the stairs, the

Assignees

• Micron Technology Inc

Inventors

• Wang Yiping
• Chen Jiewei
• Howder Collin

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title