Bare-die smart bridge connected with copper pillars for system-in-package apparatus

Patent metadata

Field	Value
Publication number	US-12406925-B2
Application number	US-202117555219-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Dec 29, 2016
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

First claim

The invention claimed is:

1. A system-in-package apparatus, comprising:
a semiconductive bridge in a molding compound, the semiconductive bridge having a top surface, a bottommost surface, a first side between the top surface and the bottommost surface, and a second side between the top surface and the bottommost surface, wherein the bottommost surface of the semiconductive bridge is at a same level as a bottommost surface of the molding compound;
a first plurality of interconnects laterally adjacent to the first side of the semiconductive bridge;
a second plurality of interconnects laterally adjacent to the second side of the semiconductive bridge;
a first IC device electrically coupled to the top surface of the semiconductive bridge, and the first IC device electrically coupled to the first plurality of interconnects;
a second IC device electrically coupled to the top surface of the semiconductive bridge, and the second IC device electrically coupled to the second plurality of interconnects;
a capping material between and in contact with the first IC device and the second IC device, the capping material between the first IC device and the top surface of the semiconductive bridge, and the capping material between the second IC device and the top surface of the semiconductive bridge;
a first plurality of bumps beneath the bottommost surface of the semiconductive bridge, the first plurality of bumps within the first side and the second side of the semiconductive bridge;
a second plurality of bumps beneath the first plurality of interconnects; and
a third plurality of bumps beneath the second plurality of interconnects.

2. The system-in-package apparatus of claim 1 , wherein the first plurality of interconnects is in a first interconnect package, and the second plurality of interconnects is in a second interconnect package.

3. The system-in-package apparatus of claim 1 , wherein the first plurality of interconnects is a first plurality of via bars, and the second plurality of interconnects is a second plurality of via bars.

4. The system-in-package apparatus of claim 1 , further comprising:
a third device electrically coupled to the top surface of the semiconductive bridge, wherein the third device is between the first IC device and the second IC device.

5. The system-in-package apparatus of claim 4 , wherein the third device is a passive device.

6. The system-in-package apparatus of claim 1 , wherein the first IC device is electrically coupled to the top surface of the semiconductive bridge and to the to the first plurality of interconnects by a first plurality of pillars, and wherein the second IC device is electrically coupled to the top surface of the semiconductive bridge and to the to the second plurality of interconnects by a second plurality of pillars.

7. A system-in-package apparatus, comprising:
a semiconductive bridge in a molding compound, the semiconductive bridge having a top surface, a bottommost surface, a first side between the top surface and the bottommost surface, and a second side between the top surface and the bottommost surface, wherein the bottommost surface of the semiconductive bridge is at a same level as a bottommost surface of the molding compound;
a first interconnect laterally adjacent to the first side of the semiconductive bridge;
a second interconnect laterally adjacent to the second side of the semiconductive bridge;
a first IC device electrically coupled to the top surface of the semiconductive bridge, and the first IC device electrically coupled to the first interconnect;
a second IC device electrically coupled to the top surface of the semiconductive bridge, and the second IC device electrically coupled to the second interconnect;
a capping material between and in contact with the first IC device and the second IC device, the capping material between the first IC device and the top surface of the semiconductive bridge, and the capping material between the second IC device and the top surface of the semiconductive bridge;
a first bump beneath the bottommost surface of the semiconductive bridge, the first bump within the first side and the second side of the semiconductive bridge;
a second bump beneath the first interconnect; and
a third bump beneath the second interconnect.

8. The system-in-package apparatus of claim 7 , wherein the first interconnect is in a first interconnect package, and the second interconnect is in a second interconnect package.

9. The system-in-package apparatus of claim 7 , wherein the first interconnect is a first via bar, and the second interconnect is a second via bar.

10. The system-in-package apparatus of claim 7 , further comprising:
a third device electrically coupled to the top surface of the semiconductive bridge, wherein the third device is between the first IC device and the second IC device.

11. The system-in-package apparatus of claim 10 , wherein the third device is a passive device.

12. The system-in-package apparatus of claim 7 , wherein the first IC device is electrically coupled to the top surface of the semiconductive bridge and to the to the first interconnect by a first pillar, and wherein the second IC device is electrically coupled to the top surface of the semiconductive bridge and to the to the second interconnect by a second pillar.

13. A system-in-package apparatus, comprising:
a smart die in a molding compound, the smart die having a top surface, a bottom bottommost surface, a first side between the top surface and the bottommost surface, and a second side between the top surface and the bottommost surface, wherein the bottom bottommost surface of the smart die is at a same level as a bottommost surface of the molding compound;
a first plurality of interconnects laterally adjacent to the first side of the smart die;
a second plurality of interconnects laterally adjacent to the second side of the smart die;
a processor logic die electrically coupled to the top surface of the smart die, and the processor logic die electrically coupled to the first plurality of interconnects;
a memory die electrically coupled to the top surface of the smart die, and the memory die electrically coupled to the second plurality of interconnects;
a capping material between and in contact with the processor logic die and the memory die, the capping material between the processor logic die and the top surface of the smart die, and the capping material between the memory die and the top surface of the smart die;
a first plurality of bumps beneath the bottommost surface of the smart die, the first plurality of bumps within the first side and the second side of the smart die;
a second plurality of bumps beneath the first plurality of interconnects; and
a third plurality of bumps beneath the second plurality of interconnects.

14. The system-in-package apparatus of claim 13 , wherein the first plurality of interconnects is in a first interconnect package, and the second plurality of interconnects is in a second interconnect package.

15. The system-in-package apparatus of claim 13 , wherein the first plurality of interconnects is a first plurality of via bars, and the second plurality of interconnects is a second plurality of via bars.

16. The system-in-package apparatus of claim 13 , further comprising:
a passive device electrically coupled to the top surface of the smart die, wherein the passive device is between the processor logic die and the memory die.

17. The system-in-package apparatus of claim 13 , wherein the processor logic die is electrically coupled to the top surface of th

Assignees

• Intel Corp

Inventors

• Seidemann Georg
• Wagner Thomas
• Wolter Andreas
• Waidhas Bernd

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title