Self-selecting memory device, memory system having the same, and operating method thereof

Patent metadata

Field	Value
Publication number	US-12406725-B2
Application number	US-202318334790-A
Country	US
Kind code	B2
Filing date	Jun 14, 2023
Priority date	Nov 28, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.

First claim

What is claimed is:

1. An operating method of a self-selecting memory device, comprising
applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width; and
applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width,
wherein the first write pulse and the second write pulse have substantially opposite polarities,
wherein the first pulse width is longer than the second pulse width,
wherein each of the first memory cell and the second memory cell comprises:
a lower electrode;
a first chalcogenide layer disposed above the lower electrode;
an intermediate electrode disposed above the first chalcogenide layer;
a second chalcogenide layer disposed above the intermediate electrode; and
an upper electrode disposed above the second chalcogenide layer,

wherein one of the first chalcogenide layer and the second chalcogenide layer includes a storage material, and the other of the first chalcogenide layer and the second chalcogenide layer includes a selection material, and
wherein the first chalcogenide layer is in direct contact with the lower electrode and the intermediate electrode, and the second chalcogenide layer is in direct contact with the intermediate electrode and the upper electrode.

2. The operating method of claim 1 , wherein each of the first memory cell and the second memory cell includes a phase-change material.

3. The operating method of claim 1 , wherein the storage material includes:
at least two elements among Ge, Te, and Sb; and
at least one element among C, N and O.

4. The operating method of claim 1 , wherein the selection material includes:
at least two elements among Ge, As, and Se; and
at least one element among Si, In, Te, Sn, Ga, and N.

5. The operating method of claim 1 ,
wherein the first write pulse corresponding to the first state and a first read pulse corresponding to the first state have substantially the same polarities,
wherein the second write pulse corresponding to the second state and a second read pulse corresponding to the second state have substantially opposite polarities.

6. The operating method of claim 1 , wherein the first pulse width is longer than 100 ns.

7. The operating method of claim 1 , wherein the second pulse width is shorter than 100 ns.

8. The operating method of claim 1 , wherein:
the first state indicates a crystallization state, and
the second state indicates an amorphous state.

9. A self-selecting memory device, comprising:
word-lines;
bit-lines; and
a plurality of memory cells connected between the word-lines and the bit-lines,
wherein each of the plurality of memory cells stores data in one of a first state indicating a crystallization state and a second state indicating an amorphous state,
wherein a polarity direction of a second write pulse applied to a corresponding word-line and a corresponding bit-line when data is stored in the second state and a polarity direction of a first write pulse applied to a corresponding word-line and a corresponding bit-line when data is stored in the first state are substantially opposite to each other,
wherein a pulse width of the second write pulse is shorter than a pulse width of the first write pulse,
wherein each of the plurality of memory cells includes:
a lower electrode connected to a corresponding bit-line;
a first chalcogenide layer disposed above the lower electrode;
an intermediate electrode layer disposed above the first chalcogenide layer;
a second chalcogenide layer disposed above the intermediate electrode; and
an upper electrode disposed above the second chalcogenide layer, and connected to a corresponding word-line,

wherein one of the first chalcogenide layer and the second chalcogenide layer includes a storage material, and the other of the first chalcogenide layer and the second chalcogenide layer includes a selection material, and
wherein the first chalcogenide layer is in direct contact with the lower electrode and the intermediate electrode, and the second chalcogenide layer is in direct contact with the intermediate electrode and the upper electrode.

10. The self-selecting memory device of claim 9 , wherein each of the plurality of memory cells includes a chalcogenide layer having a storage material or a selection material.

11. The self-selecting memory device of claim 9 ,
wherein each of the plurality of memory cells is implemented with an ovonic threshold switching (OTS) material and a phase-change storage material (PCS) material,
wherein the PCS material comprises a germanium-antimony-tellurium alloy.

12. The self-selecting memory device of claim 9 , wherein:
polarities for a first read pulse corresponding to the first state and the first write pulse corresponding to the first state are substantially the same, and
polarities for a second read pulse corresponding to the second state and a second write pulse corresponding to the second state are substantially opposite to each other.

13. A memory system, comprising:
at least one self-selecting memory device; and
a controller configured to control the at least one self-selecting memory device,
wherein the at least one self-selecting memory device adjusts a crystalline phase of a memory cell by changing a shape of the write pulse when a write voltage is applied,
wherein polarities of the write pulse and a read pulse are different according to a first state indicating a crystalline state and a second state indicating an amorphous state,
wherein the memory cell comprises:
a lower electrode;
a first chalcogenide layer disposed above the lower electrode;
an intermediate electrode disposed above the first chalcogenide layer;
a second chalcogenide layer disposed above the intermediate electrode; and
an upper electrode disposed above the second chalcogenide layer,

wherein one of the first chalcogenide layer and the second chalcogenide layer includes a storage material, and the other of the first chalcogenide layer and the second chalcogenide layer includes a selection material, and
wherein the first chalcogenide layer is in direct contact with the lower electrode and the intermediate electrode, and the second chalcogenide layer is in direct contact with the intermediate electrode and the upper electrode.

14. The memory system of claim 13 , wherein:
polarities for a first write pulse and a first read pulse in the first state are substantially the same, and
polarities for a second write pulse and a second read pulse in the second state are substantially opposite to each other.

15. The memory system of claim 14 , wherein:
a write pulse width of the first write pulse is longer than a reference value, and
a write pulse width of the second write pulse is shorter than the reference value.

16. The memory system of claim 15 , wherein the reference value is 100 ns.

17. The memory system of claim 13 , wherein:
the memory cell comprises a germanium-antimony-tellurium alloy,
each of the plurality of memory cells includes a selenium-rich region formed therein in a direction in which electrons move when polarities of the write pulse and the read pulse are applied in substantially opposite directions.

Assignees

• Samsung Electronics Co Ltd

Inventors

• CHOI Soyeon
• Wu Zhe
• Kim Chungman
• Yu Seunggeun
• Lee Jabin

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title