Method for fabricating semiconductor device and semiconductor device

Patent metadata

Field	Value
Publication number	US-12402295-B2
Application number	US-202217974540-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Nov 4, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

Embodiments provide a method for fabricating a semiconductor device and the semiconductor device. The method includes: providing a semiconductor substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, where a pattern density of the first pattern mask is greater than a pattern density of the second pattern mask, and the first height is greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate having a first region and a second region;
forming an initial mask layer on an upper surface of the substrate;
providing a first pattern mask, forming the first pattern mask in the initial mask layer on the first region, and forming the second pattern mask in the initial mask layer on the second region, the pattern density of the first pattern mask being greater than the pattern density of the second pattern mask;
partially etching the second pattern mask, such that a height of the second pattern mask is less than a height of the first pattern mask; and
etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

2. The method according to claim 1 , wherein the first region is a memory array region, and the second region is a peripheral circuit region.

3. The method according to claim 1 , wherein the initial mask layer comprises a second initial mask layer and a first initial mask layer stacked sequentially from bottom to top; and
the forming the first pattern mask in the initial mask layer on the first region, and forming the second pattern mask in the initial mask layer on the second region comprises:
patterning the first initial mask layer based on the first pattern mask to form a first initial mask;
etching the second initial mask layer based on the first initial mask to form the first pattern mask and the second pattern mask; and
removing the first initial mask.

4. The method according to claim 1 , wherein the partially etching the second pattern mask comprises:
depositing an intermediate dielectric material to form an intermediate dielectric layer filling the first pattern mask and the second pattern mask;
providing a second pattern mask, and forming a mask pattern exposing the second pattern mask in the intermediate dielectric layer on the second region;
etching and removing part of the second pattern mask based on the mask pattern; and
removing the intermediate dielectric layer.

5. The method according to claim 1 , wherein the patterning the initial mask layer comprises:
providing a third pattern mask, and forming, on the initial mask layer, a mask pattern exposing the initial mask layer of the second region;
partially etching the initial mask layer based on the mask pattern, such that a height of the initial mask layer of the second region is smaller than a height of the initial mask layer of the first region; and
providing a fourth pattern mask, forming the first pattern mask in the initial mask layer of the first region, and forming the second pattern mask in the initial mask layer of the second region, the pattern density of the first pattern mask being greater than the pattern density of the second pattern mask.

6. The method according to claim 1 , wherein the substrate comprises a base substrate and a stack structure on the base substrate;
wherein the stack structure comprises a first sacrificial layer, a first support layer, a second sacrificial layer and a second support layer stacked in sequence from bottom to top.

7. The method according to claim 6 , wherein the first pattern mask is a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the base substrate.

8. The method according to claim 7 , wherein the etching the substrate based on the first pattern mask and the second pattern mask, and transferring the pattern of the first pattern mask to the first region comprises:
etching the second support layer, the second sacrificial layer, the first support layer and the first sacrificial layer in sequence based on the first pattern mask, to transfer the capacitor hole pattern into the stack structure, and forming, in the stack structure, a plurality of capacitor holes and an etching pillar between adjacent two of the plurality of capacitor holes;
wherein the plurality of capacitor holes expose part of the contact structure.

9. The method according to claim 8 , further comprising:
removing the first pattern mask after the plurality of capacitor holes are formed.

10. The method according to claim 9 , further comprising:
processing the etching pillar to form a capacitor structure.

11. The method according to claim 10 , wherein the processing the etching pillar to form the capacitor structure comprises:
forming a first electrode layer on an inner wall of each of the plurality of capacitor holes and a surface of the etching pillar respectively;
forming a first opening in the second support layer;
removing the second sacrificial layer by means of the first opening;
forming a second opening in the first support layer;
removing the first sacrificial layer by means of the second opening; and
sequentially depositing a dielectric layer and a second electrode layer on a surface of the first electrode layer to form the capacitor structure.

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Bai Shijie

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/408

  characterised by their sizes, orientations, dispositions, behaviours or shapes · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title