Dynamic voltage and frequency scaling for image-sensor applications

Patent metadata

Field	Value
Publication number	US-12401921-B2
Application number	US-202218556482-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Apr 26, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

An imaging device having a digital circuit block therein subjected to in-frame DVFS during a frame sequence of the sensing operating mode. In an example embodiment, the in-frame DVFS causes a higher power-supply voltage and a higher clock frequency to be supplied to the digital circuit block during read periods of the frame sequence, and a lower power-supply voltage and a lower clock frequency to be supplied to the digital circuit block during V-blanking periods of the frame sequence. The lower power-supply voltage and clock frequency are selected to be sufficient for the digital circuit block to support the pertinent functions thereof during the V-blanking periods without adversely impacting performance. For example, the lower power-supply voltage is sufficient for a SRAM of the digital circuit block to retain data therein. Beneficially, the in-frame DVFS enables the imaging device to perform motion detection while consuming very little power.

First claim

What is claimed is:

1. An apparatus, comprising an imaging device that comprises:
an electronic controller configured to control one-frame operation of the imaging device in response to a host command, the one-frame operation including at least a read period and a V-blanking period; and
a power-supply regulator configured to selectively supply a first non-zero voltage and a second non-zero voltage to a digital circuit block of the imaging device; and
wherein the imaging device is configured to subject the digital circuit block to dynamic voltage scaling within the one-frame operation such that the first non-zero voltage is supplied to the digital circuit block during the read period, and the second non-zero voltage is supplied to the digital circuit block during the V-blanking period.

2. The apparatus of claim 1 , wherein the power-supply regulator comprises a low-dropout regulator and a power gate connected in parallel to each other between a power-supply terminal of the imaging device and the digital circuit block.

3. The apparatus of claim 1 , wherein the power-supply regulator is configured to cause an absolute value of the second non-zero voltage to be smaller than an absolute value of the first non-zero voltage.

4. The apparatus of claim 3 ,
wherein the digital circuit block includes a static random-access memory (SRAM); and
wherein the second non-zero voltage enables the SRAM to perform a data retention operation therein.

5. The apparatus of claim 4 , wherein the second non-zero voltage is insufficient for the SRAM to perform a data read operation or a data write operation therein.

6. The apparatus of claim 1 , further comprising one or more oscillators configured to supply a selected one of a first clock frequency and a second clock frequency to the digital circuit block; and
wherein the imaging device is further configured to subject the digital circuit block to dynamic frequency scaling within the one-frame operation such that the first clock frequency is supplied to the digital circuit block during the read period, and the second clock frequency is supplied to the digital circuit block during the V-blanking period.

7. The apparatus of claim 6 ,
wherein the one-frame operation includes a shutter period; and
wherein the dynamic voltage scaling and the dynamic frequency scaling within the one-frame operation are configured to cause the first non-zero voltage and the first clock frequency to be supplied to the digital circuit block during the shutter period.

8. The apparatus of claim 6 ,
wherein the one-frame operation includes an exposure period; and
wherein the dynamic voltage scaling and the dynamic frequency scaling within the one-frame operation are configured to cause the first non-zero voltage and the first clock frequency to be supplied to the digital circuit block during the exposure period.

9. The apparatus of claim 6 , wherein the one or more oscillators are configured to stop generating the first clock frequency during the V-blanking period.

10. The apparatus of claim 6 , wherein a ratio of the first clock frequency and the second clock frequency is larger than 300.

11. The apparatus of claim 6 , wherein the imaging device is configurable to operate in a selected one of a plurality of operating modes including a first mode and a different second mode, the first mode including a sequence of one-frame operations.

12. The apparatus of claim 11 , wherein the power-supply regulator is configured to continuously supply the first non-zero voltage to the digital circuit block during the second mode.

13. The apparatus of claim 12 , wherein the one or more oscillators are configured to continuously supply the first clock frequency to the digital circuit block during the second mode.

14. The apparatus of claim 11 , wherein the one or more oscillators are configured to continuously supply the first clock frequency to the digital circuit block during the second mode.

15. The apparatus of claim 6 ,
wherein the imaging device further comprises a pixel array and an analog-to-digital-converter (ADC) circuit connected to the pixel array; and
wherein the one or more oscillators are configured to supply a third clock frequency to the ADC circuit, the third clock frequency being greater than the first clock frequency.

16. The apparatus of claim 15 , wherein the third clock frequency is an integer multiple of the first frequency.

17. The apparatus of claim 15 , wherein the one or more oscillators are configured to:
supply the third clock frequency to the ADC circuit during the read period; and
stop generating the third clock frequency during the V-blanking period.

18. The apparatus of claim 1 , wherein the electronic controller includes the digital circuit block.

19. An apparatus, comprising an imaging device that comprises:
an electronic controller configured to control one-frame operation of the imaging device in response to a host command, the one-frame operation including at least a read period and a V-blanking period;
one or more oscillators configured to supply a selected one of a first clock frequency and a second clock frequency to a digital circuit block of the imaging device; and
wherein the imaging device is configured to subject the digital circuit block to dynamic frequency scaling within the one-frame operation such that the first clock frequency is supplied to the digital circuit block during the read period, and the second clock frequency is supplied to the digital circuit block during the V-blanking period.

20. A method implemented in an imaging device, the method comprising:
controlling, with an electronic controller, one-frame operation of the imaging device in response to a host command, the one-frame operation including at least a read period and a V-blanking period;
selectively supplying, with a power-supply regulator, a first non-zero voltage and a second non-zero voltage to a digital circuit block of the imaging device;
supplying, with one or more oscillators, a selected one of a first clock frequency and a second clock frequency to the digital circuit block; and
subjecting the digital circuit block to dynamic voltage and frequency scaling (DVFS) within the one-frame operation, said DVFS comprising supplying the first non-zero voltage and the first clock frequency to the digital circuit block during the read period, and supplying the second non-zero voltage and the second clock frequency to the digital circuit block during the V-blanking period.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Childs John Steven
• Pude Mark
• Murakami Hirotaka
• Childs Robert James
• Cziesler Cody

Classifications

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/325

  Power saving in peripheral device · CPC title