Image device and operating method thereof

Patent metadata

Field	Value
Publication number	US-11134189-B2
Application number	US-202016743102-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jun 17, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

An image device may include a clock generator to generate a first output clock of a first frequency, a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information, a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, and a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer. The link layer transmits the control signal to the clock generator based on the frequency change command. The vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output.

First claim

What is claimed is:

1. An image device, comprising:
a clock generator to generate a first output clock of a first frequency;
a link layer circuit to generate a control signal for changing the first frequency and output first parallel data including first frame information;
a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, the second frequency being different from the first frequency; and
a frequency changing circuit to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer circuit, wherein:
the link layer circuit transmits the control signal to the clock generator based on the frequency change command, and
the vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer circuit to a second time point at which second parallel data is output, the second parallel data including second frame information subsequent to the first frame information.

2. The image device as claimed in claim 1 , wherein
the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, and wherein:
the PLL circuit generates a first PLL clock of the first frequency, and
the clock gating circuit generates the first output clock by controlling output of the first PLL clock.

3. The image device as claimed in claim 2 , wherein
the control signal includes a frequency division control signal and a clock enable signal, and wherein:
the frequency division control signal changes the first frequency of the first PLL clock to the second frequency, and
when the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output.

4. The image device as claimed in claim 3 , wherein the clock gating circuit includes an inverter, a selector, a first flip-flop, and a second flip-flop, wherein:
the inverter receives the first PLL clock and outputs an inverted first PLL clock,
the first flip-flop receives the clock enable signal via a first input terminal of the first flip-flop and receives the inverted first PLL clock via a second input terminal of the first flip-flop,
the second flip-flop includes a third input terminal connected to a first output terminal of the first flip-flop, receives the inverted first PLL clock via a fourth input terminal of the second flip-flop, and outputs a selection signal via a third output terminal of the second flip-flop, and
the selector receives the first PLL clock via a first input selection terminal of the selector, receives a ground voltage via a second input selection terminal of the selector, selects one of the first PLL clock and the ground voltage, and outputs the selected one as the first output clock.

5. The image device as claimed in claim 3 , wherein:
the clock enable signal is deactivated at the second time point when is later than the first time point by a first period,
the frequency division control signal changes the first frequency of the first PLL clock at a third time point when is later than the second time point by a second period, and
the clock enable signal is activated at a fourth time point when is later than the third time point by a third period.

6. The image device as claimed in claim 5 , wherein:
the link layer circuit is operated based on a first word clock, and
the first period is thirty times of a clock cycle of the first word clock.

7. The image device as claimed in claim 5 , wherein the third period is 75 microseconds or more.

8. The image device as claimed in claim 1 , further comprising a first peripheral circuit to operate in a first bandwidth, wherein
the detector senses whether there is frequency collision between the first frequency and the first bandwidth and transmits the collision avoidance command to the frequency changing circuit when the frequency collision is sensed.

9. The image device as claimed in claim 8 , wherein the second frequency does not collide with the first bandwidth.

10. An image device, comprising:
a detector to generate a collision avoidance command;
a frequency changing circuit to receive the collision avoidance command from the detector and generate a frequency change command;
a link layer circuit to receive the frequency change command from the frequency changing circuit, generate a control signal based on the frequency change command, and output first parallel data including first frame information; and
a clock generator to receive the control signal from the link layer circuit and generate a first output clock of a first frequency, wherein:
the first frequency is changed to a second frequency during a vertical blanking time, the second frequency being different from the first frequency, and
the vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer circuit to a second time point at which second parallel data is output, the second parallel data including second frame information subsequent to the first frame information.

11. The image device as claimed in claim 10 , wherein
the clock generator includes a phase-locked loop (PLL) circuit and a clock gating circuit, wherein:
the PLL circuit generates a first PLL clock of the first frequency,
the clock gating circuit generates the first output clock by controlling output of the first PLL clock, and
the control signal includes a frequency division control signal and a clock enable signal, and wherein:
the frequency division control signal changes the first frequency of the first PLL clock, and
when the clock enable signal is deactivated, the first PLL clock is blocked by the clock gating circuit such that the first output clock is not output.

12. The image device as claimed in claim 11 , wherein the clock gating circuit includes an inverter, a selector, a first flip-flop, and a second flip-flop, and wherein:
the inverter receives the first PLL clock and outputs an inverted first PLL clock,
the first flip-flop receives the clock enable signal via a first input terminal of the first flip-flop and receives the inverted first PLL clock via a second input terminal of the first flip-flop,
the second flip-flop includes a third input terminal connected to a first output terminal of the first flip-flop, receives the inverted first PLL clock via a fourth input terminal of the second flip-flop, and outputs a selection signal via a third output terminal of the second flip-flop, and
the selector receives the first PLL clock via a first input selection terminal, receives a ground voltage via a second input selection terminal of the selector, and selects one of the first PLL clock and the ground voltage, and outputs the selected one as the first output clock.

13. The image device as claimed in claim 11 , wherein the clock enable signal is deactivated at a second time point when is later than the first time point by a first period, and
the frequency division control signal changes the first frequency of the first PLL clock at a third time point when is later than the second time point by a second period, and
the clock enable signal is activated at a fourth time point when is later than the third time point by a third period.

14. The image device as claimed in claim 13 , wherein:
the link layer circuit is operated based on a first word clock, and
the first period is thirty times of a clock cycle of the first word clock.

15. The image device as claimed in claim 13 , wherein the third perio

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Ji Un
• Kim Ki Woon
• Kim Chae Ryung
• Kim Ho Young
• Yun Eun Seung
• Lee Han Soo
• Cha Gyeong Han

Classifications

• H04N23/665 Primary

  involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals · CPC title

• H04N25/617

  for reducing electromagnetic interference, e.g. clocking noise · CPC title

• H04N23/81 Primary

  for suppressing or minimising disturbance in the image signal generation · CPC title

• H10F39/12

  Image sensors · CPC title

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title