Circuits and methods for controlling a voltage of a semiconductor substrate

Patent metadata

Field	Value
Publication number	US-12401359-B2
Application number	US-202418754010-A
Country	US
Kind code	B2
Filing date	Jun 25, 2024
Priority date	Jun 29, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.

First claim

What is claimed is:

1. An electronic device, comprising:
a gallium nitride (GaN)-based top layer attached to a semiconductor-based bottom layer;
a switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node;
a first transistor formed on the GaN-based top layer and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor-based bottom layer, the first drain terminal connected to the first source node and the first gate terminal coupled directly to the second source node; and
a second transistor formed on the GaN-based top layer and including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the semiconductor-based bottom layer, the second drain terminal connected to the second source node and the second gate terminal coupled directly to the first source node.

2. The electronic device of claim 1 , further comprising:
a first diode including a first anode and a first cathode, the first anode connected to the semiconductor-based bottom layer and the first cathode connected to the first source node; and
a second diode including a second anode and a second cathode, the second anode connected to the semiconductor-based bottom layer and the second cathode connected to the second source node.

3. The electronic device of claim 2 , wherein the first and second diodes are monolithically formed on the GaN-based top layer.

4. The electronic device of claim 2 , wherein the semiconductor first and second diodes are silicon carbide (SiC)-based.

5. The electronic device of claim 4 , wherein the GaN-based top layer attached to the semiconductor-based bottom layer is formed on a first die, and the first and second diodes are formed on a second die, wherein the first and second die are co-packaged in a unitary semiconductor package.

6. The electronic device of claim 1 , wherein the first and second transistors are enhancement-mode field effect transistors (FETs).

7. The electronic device of claim 1 , wherein the first and the second transistors each comprise two or more field effect transistors (FETs) connected in series.

8. An electronic device, comprising:
a semiconductor substrate;
a switch formed on the semiconductor substrate and including a first source node, a second source node and a common drain node;
a first transistor formed on the semiconductor substrate and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to the second source node; and
a second transistor formed on the semiconductor substrate and including a second source terminal, a second drain terminal and a second gate terminal, wherein the second transistor is arranged to couple the second source node to the semiconductor substrate when a voltage at the first source node is greater than a voltage at the semiconductor substrate.

9. The electronic device of claim 8 , wherein the semiconductor substrate comprises GaN.

10. The electronic device of claim 8 , wherein the first transistor is arranged to couple the first source node to the semiconductor substrate in response to a voltage at the second source node being at a voltage that is higher than a voltage of the semiconductor substrate.

11. The electronic device of claim 9 , further comprising:
a first diode including a first anode and a first cathode, the first anode connected to the semiconductor substrate and the first cathode connected to the first source node; and
a second diode including a second anode and a second cathode, the second anode connected to the substrate and the second cathode connected to the second source node.

12. The electronic device of claim 11 , wherein the first and second diodes are monolithically formed on the semiconductor substrate.

13. The electronic device of claim 11 , wherein the first and second diodes are formed on one or more silicon carbide (SiC) substrates.

14. The electronic device of claim 8 , wherein the first and second transistors each comprise two or more field effect transistors (FETs).

15. The electronic device of claim 8 , wherein the first and second transistors are enhancement-mode field effect transistors (FETs).

16. A method of forming a circuit, the method comprising:
forming a semiconductor substrate;
forming a bidirectional transistor on the semiconductor substrate, the bidirectional transistor including a first source node, a second source node and a common drain node;
forming a first transistor on the semiconductor substrate, the first transistor including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to the second source node; and
forming a second transistor on the semiconductor substrate, the second transistor including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the semiconductor substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state when a voltage at the first source node is greater than a voltage at the semiconductor substrate.

17. The method of claim 16 , further comprising:
forming a first diode including a first anode and a first cathode, the first anode connected to the semiconductor substrate and the first cathode connected to the first source node; and
forming a second diode including a second anode and a second cathode, the second anode connected to the semiconductor substrate and the second cathode connected to the second source node.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Sharma Santosh
• Kinzer Daniel M
• Tzeng Ren Huei

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H03K17/08142

  in field-effect transistor switches · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title