Circuits and methods for controlling a voltage of a semiconductor substrate

Patent metadata

Field	Value
Publication number	US-11870429-B2
Application number	US-202218064185-A
Country	US
Kind code	B2
Filing date	Dec 9, 2022
Priority date	Jun 29, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An electronic device includes a semiconductor substrate and a bidirectional transistor switch formed on the substrate, the bidirectional switch including a first source node, a second source node and a common drain node. A first transistor is formed on the substrate and includes a first source terminal, a first drain terminal and a first gate terminal, wherein the first source terminal is connected to the substrate, the first drain terminal is connected to the first source node and the first gate terminal is connected to the second source node. A second transistor is formed on the substrate and includes a second source terminal, a second drain terminal and a second gate terminal, wherein the second source terminal is connected to the substrate, the second drain terminal is connected to the second source node and the second gate terminal is connected to the first source node.

First claim

What is claimed is:

1. An electronic device, comprising:
a gallium nitride (GaN) substrate comprising a GaN-based top layer attached to a silicon-based bottom layer;
a bidirectional transistor switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node;
a first transistor formed on the GaN-based top layer and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the silicon-based bottom layer, the first drain terminal connected to the first source node and the first gate terminal coupled to the second source node;
a second transistor formed on the GaN-based top layer and including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the silicon-based bottom layer, the second drain terminal connected to the second source node and the second gate terminal coupled to the first source node;
a third transistor formed on the GaN-based top layer and including a third drain, a third source and a third gate, the third gate connected to a voltage source, the third drain connected to the first source node and the third source connected to the second gate terminal; and
a fourth transistor formed on the GaN-based top layer and including a fourth drain, a fourth source and a fourth gate, the fourth gate connected to the voltage source, the fourth drain connected to the second source node, and the fourth source connected to the first gate terminal.

2. The electronic device of claim 1 further comprising:
a first diode including a first anode and a first cathode, the first anode connected to the silicon-based bottom layer and the first cathode connected to the first source node; and
a second diode including a second anode and a second cathode, the first anode connected to the silicon-based bottom layer and the second cathode connected to the second source node.

3. The electronic device of claim 2 wherein the first and second diodes are monolithically formed on the GaN substrate.

4. The electronic device of claim 2 wherein the first and second diodes are formed on one or more silicon carbide (SiC) substrates.

5. The electronic device of claim 1 wherein the third and fourth transistors are depletion-mode field effect transistors (FETs).

6. The electronic device of claim 1 wherein the third and fourth transistors are enhancement-mode field effect transistors (FETs).

7. The electronic device of claim 1 wherein the third and the fourth transistors each comprise two or more FETs connected in series.

8. An electronic device, comprising:
a semiconductor substrate;
a bidirectional transistor switch formed on the substrate and including a first source node, a second source node and a common drain node;
a first transistor formed on the substrate and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the substrate, the first drain terminal connected to the first source node and the first gate terminal connected to the second source node;
a second transistor formed on the substrate and including a second source terminal, a second drain terminal and a second gate terminal, wherein the second transistor is arranged to couple the second source terminal to the semiconductor substrate in response to a voltage of the first source node at a voltage that is higher than a voltage of the semiconductor substrate;
a third transistor formed on the substrate and including a third drain, a third source and a third gate, the third gate connected to a voltage source, the third drain connected to the first source node and the third source connected to the second gate terminal; and
a fourth transistor formed on the substrate and including a fourth drain, a fourth source and a fourth gate, the fourth gate connected to the voltage source, the fourth drain connected to the second source node, and the fourth source connected to the first gate terminal.

9. The electronic device of claim 8 wherein the semiconductor substrate comprises GaN.

10. The electronic device of claim 8 wherein the first transistor is arranged to couple the first source terminal to the semiconductor substrate in response to a voltage of the second source node at a voltage that is higher than a voltage of the semiconductor substrate.

11. The electronic device of claim 8 further comprising:
a first diode including a first anode and a first cathode, the first anode connected to the substrate and the first cathode connected to the first source node; and
a second diode including a second anode and a second cathode, the first anode connected to the substrate and the second cathode connected to the second source node.

12. The electronic device of claim 11 wherein the first and second diodes are monolithically formed on the substrate.

13. The electronic device of claim 11 wherein the first and second diodes are formed on one or more silicon carbide (SiC) substrates.

14. The electronic device of claim 8 wherein the third and fourth transistors are depletion-mode field effect transistors (FETs).

15. The electronic device of claim 8 wherein the third and fourth transistors are enhancement-mode field effect transistors (FETs).

16. The electronic device of claim 8 wherein the third and the fourth transistors each comprise two or more FETs connected in series.

17. A method of forming a circuit, the method comprising:
forming a semiconductor substrate;
forming a bidirectional transistor on the semiconductor substrate, the bidirectional transistor including a first source node, a second source node and a common drain node;
forming a first transistor on the substrate, the first transistor including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the substrate, the first drain terminal connected to the first source node and the first gate terminal connected to the second source node;
forming a second transistor on the substrate, the second transistor including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state in response to the first source node at a positive voltage relative to a voltage of the semiconductor substrate;
forming a third transistor on the substrate, the third transistor including a third drain, a third source, and a third gate, the third gate connected to a voltage source, the third drain connected to the first source node and the third source connected to the second gate terminal; and
forming a fourth transistor on the substrate, the fourth transistor including a fourth drain, a fourth source, and a fourth gate, the fourth gate connected to the voltage source, the fourth drain connected to the second source node, and the fourth source connected to the first gate terminal.

18. The method of claim 17 wherein the semiconductor substrate comprises GaN.

19. The method of claim 17 wherein the third and fourth transistors are depletion-mode field effect transistors (FETs).

20. The method of claim 17 wherein the third and fourth transistors are enhancement-mode field effect transistors (FETs).

Assignees

• Navitas Semiconductor Ltd

Inventors

• Sharma Santosh
• Kinzer Daniel M
• Tzeng Ren Huei

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title

• H01L29/2003

  Electricity · mapped topic

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title