Memory device and operating method of a memory device

Patent metadata

Field	Value
Publication number	US-12401353-B2
Application number	US-202318219254-A
Country	US
Kind code	B2
Filing date	Jul 7, 2023
Priority date	Sep 6, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

First claim

What is claimed is:

1. An operating method of a memory device, comprising,
receiving a read enable signal through a first node;
delaying the read enable signal using a first delay path connected between the first node and an intermediate node;
delaying the delayed signal using a second delay path connected between the intermediate node and a second node; and
generating a data strobe signal by delaying the delayed signal from the second delay path using a third delay path connected between the second node and a third node,
wherein the delaying of the delayed signal includes:
correcting, by a duty cycle corrector, a duty ratio of the delayed signal of the intermediate node using an internal clock signal pair,
selecting, by a multiplexer, the delayed signal of the intermediate node or the corrected signal from the duty cycle corrector in response to a selection signal, and
inverting, by an inverting repeater, a phase of the selected signal from the multiplexer.

2. The operating method as claimed in claim 1 , wherein the delaying of the read enable signal using the first delay path includes delaying, by a plurality of repeaters connected in series, the read enable signal, and
wherein the delaying of the delayed signal using the third delay path includes delaying by a plurality of repeaters connected in series, the delayed signal from the second delay path.

3. The operating method as claimed in claim 1 , wherein the delaying of the delayed signal using the second delay path includes inverting, by an odd number of inverters connected in series, the delayed signal from the first delay path.

4. The operating method as claimed in claim 3 , wherein the odd number of inverters is 5.

5. The operating method as claimed in claim 1 , wherein the inverting pea ter of the phase of the selected signal includes:
inverting, by an inverter, the phase of the selected signal from the multiplexer; and
delaying by a plurality of repeaters connected in series, the inverted signal.

6. The operating method as claimed in claim 1 , wherein the selecting of the delayed signal or the corrected signal includes generating the selection signal according to a set code in a mode register set.

7. The operating method as claimed in claim 1 , wherein the generating of the data strobe signal includes:
delaying, by a plurality of repeaters connected in series, the delayed signal of the second node;
splitting, by a phase splitter, phases of the delayed signal from the plurality of repeaters, and generating a clock signal and an inverted clock signal; and
selecting, by a selector, one of the clock signal and the inverted clock signal as the data strobe signal.

8. The operating method as claimed in claim 7 , wherein the splitting of the phases of the delayed signal from the plurality of repeaters includes inverting the delayed signal from the plurality of repeaters and splitting the phases of the delayed signal from the plurality of repeaters.

9. The operating method as claimed in claim 7 , wherein the selecting of one of the clock signal and the inverted clock signal includes:
selecting the clock signal in response to the inverted clock signal, or
selecting the inverted clock signal in response to the clock signal.

10. A memory device, comprising:
a first delay path connected between a first node with and an intermediate node and configured to receive a read enable signal through the first node and delay the read enable signal;
a second delay path connected between the intermediate node and a second node and configured to delay the delayed signal from the first delay path; and
a third delay path connected between the second node and a third node and configured to generate a data strobe signal by delaying the delayed signal from the second delay path,
wherein the second delay path includes:
a duty cycle corrector configured to correct a duty ratio of the delayed signal of the intermediate node using an internal clock signal pair,
a multiplexer configured to select the delayed signal of the intermediate node or the corrected signal from the duty cycle corrector in response to a selection signal, and
an inverting repeater configured to invert a phase of the selected signal from the multiplexer.

11. The memory device as claimed in claim 10 , wherein the inverting repeater includes:
an inverter configured to invert the phase of the selected signal from the multiplexer; and
a plurality of repeaters connected in series and configured to delay the inverted delayed signal.

12. The memory device as claimed in claim 10 , wherein the third delay path includes:
a plurality of repeaters connected in series and configured to delay the delayed signal of the second node;
a phase splitter configured to split phases of the delay delayed signal from the plurality of repeaters and generate a clock signal and an inverted clock signal; and
a selector configured to select one of the clock signal and the inverted clock signal as the data strobe signal.

13. The memory device as claimed in claim 12 , wherein the phase splitter is configured to invert the delayed signal from the plurality of repeaters and split phases of the in delayed signal from the plurality of repeaters.

14. A memory device, comprising:
a plurality of data strobe signal drivers;
a delay locked loop circuit configured to generate a delayed clock signal that is delay-locked to an external clock signal; and
a clock signal delay path configured to delay the delayed clock signal, generate internal clock signals, and transmit the internal signal clock signals to the plurality of data strobe signal drivers,
wherein the clock signal delay path includes:
a first delay path connected between a first node with and an intermediate node and configured to receive the delayed clock signal through the first node and delay the read delayed clock signal;
a second delay path connected between the intermediate node and a second node and configured to delay the delayed signal from the first delay path; and
a third delay path connected between the second node and a third node and configured to generate a data strobe signal by delaying the delayed signal from the second delay path, and

wherein the second delay path is configured to invert a phase of the delayed signal from the first delay path.

15. The memory device as claimed in claim 14 , wherein the second delay path includes:
a duty cycle corrector configured to correct a duty ratio of the delayed signal of the intermediate node using an internal clock signal pair;
a multiplexer configured to select the delayed signal of the intermediate node or the corrected signal from the duty cycle corrector in response to a selection signal; and
an inverting repeater configured to invert the phase of the selected signal from the multiplexer.

16. The memory device as claimed in claim 15 , wherein the inverting repeater includes:
an inverter configured to invert the phase of the selected signal from the multiplexer; and
a plurality of repeaters connected in series and configured to delay the inverted signal.

17. The memory device as claimed in claim 14 , wherein the third delay path includes:
a plurality of repeaters connected in series and configured to delay the delayed signal of the second node;
a phase splitter configured to split phases of the delay delayed signal from the plurality of repeaters and generate a clock signal and an inverted clock signal; and
a selector configured to select one of the clock signal and the inverted clock signal as a data strobe signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Mingyu
• Cho Youngchul
• Park Seungjin
• Choi Youngdon
• Choi Junghwan

Classifications

• H03K5/065

  using dispersive delay lines · CPC title

• H03K5/1508

  using a plurality of delay lines · CPC title

• H03K5/1506

  with parallel driven output stages; with synchronously driven series connected output stages · CPC title

• H03K5/05

  by the use of clock signals or other time reference signals · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title