Apparatus for generating a plurality of phase-shifted clock signals, electronic system, base station and mobile device

Patent metadata

Field	Value
Publication number	US-11183993-B2
Application number	US-201916724564-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 23, 2019
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

First claim

What is claimed is:

1. An apparatus for generating a plurality of phase-shifted clock signals, comprising:
a first input node configured to receive a first reference clock signal;
a second input node configured to receive a second reference clock signal;
a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals; and
a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal, wherein input nodes of a first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node, wherein output nodes of a last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes, wherein the cascade of clock generation circuits comprises at least one active clock generation circuit and at least one passive clock generation circuit that are coupled alternatingly in series,
wherein the active clock generation circuit is an injection-locked oscillator, and the passive clock generation circuit is an RC polyphase filter.

2. The apparatus of claim 1 , wherein the plurality of phase-shifted clock signals is four or more phase-shifted clock signals.

3. The apparatus of claim 1 , wherein the plurality of phase-shifted clock signals are phase shifted by a predetermined phase shift with respect to each other.

4. The apparatus of claim 1 , wherein the at least one passive clock generation circuit comprises exclusively passive electronic elements.

5. The apparatus of claim 1 , wherein the at least one active clock generation circuit comprises at least one active electronic element.

6. The apparatus of claim 1 , wherein the cascade of clock generation circuits comprises a plurality of passive clock generation circuits and a plurality of active clock generation circuits coupled alternatingly in series.

7. The apparatus of claim 1 , wherein the cascade of clock generation circuits comprises at least two passive clock generation circuits coupled in series, wherein the cascade of clock generation circuits comprises at least two active clock generation circuits coupled in series.

8. The apparatus of claim 1 , wherein the cascade of coupled clock generation circuits comprises two clock generation circuits, wherein the first clock generation circuit of the cascade of clock generation circuits is a passive circuit, and wherein the last clock generation circuit of the cascade of clock generation circuits is an active circuit.

9. The apparatus of claim 1 , wherein the cascade of coupled clock generation circuits comprises at least three clock generation circuits.

10. The apparatus of claim 1 , wherein the number of polyphases of the RC polyphase filter is equal to the number the plurality of phase-shifted clock signals.

11. The apparatus of claim 1 , wherein the second reference clock signal is inverted with respect to the first reference clock signal.

12. An electronic system, comprising:
the apparatus according to claim 1 ; and
at least one electronic device coupled to at least part of the plurality of output nodes for receiving at least part of the plurality of phase-shifted clock signals.

13. The electronic system of claim 12 , wherein the at least one electronic device is one of a digital-to-analog converter, an analog-to-digital converter and a radio frequency mixer.

14. The electronic system of claim 12 , wherein the wherein the electronic system is one of a consumer product, a base station, a mobile device, a router, an ethernet switch, a transmitter, a receiver and a transceiver.

Assignees

• Intel Corp

Inventors

• Shin Hundo
• Azadet Kameran
• Clara Martin
• Gruber Daniel

Classifications

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title

• H03K5/1506 Primary

  with parallel driven output stages; with synchronously driven series connected output stages · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H04W88/08

  Access point devices · CPC title