Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12400981-B2
Application number	US-202318176189-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Jun 20, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a first structure on a first substrate;
forming a first bonded body by coupling a supporting substrate lower in rigidity than the first substrate to a first principal surface of the first substrate, the first structure is formed on the first principal surface;
removing the first substrate from the first bonded body;
forming a second structure on a second substrate;
forming a third structure on a third substrate;
forming a second bonded body by coupling a second principal surface of the second substrate to a third principal surface, the second structure is formed on the second principal surface, the third structure is formed on the third principal surface;
removing the second substrate from the second bonded body;
forming a third bonded body by coupling a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body; and
removing the supporting substrate from the third bonded body.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein
a Young's modulus of the supporting substrate is lower than a Young's modulus of the first substrate.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein
a geometrical moment of inertia of the supporting substrate is smaller than a geometrical moment of inertia of the first substrate.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein
a thickness of the supporting substrate is smaller than a thickness of the first substrate.

5. The method for manufacturing a semiconductor device according to claim 1 , further comprising
extending the supporting substrate in a plane direction between forming the first bonded body and forming the third bonded body.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein
the first structure includes a first memory cell array structure,
the second structure includes a circuit structure, and
the third structure includes a second memory cell array structure.

7. The method for manufacturing a semiconductor device according to claim 1 , wherein the bonding to form the first bonded body is performed by heating and pressurizing.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein the bonding to form the first bonded body is performed using adhesive or direct bonding.

9. The method for manufacturing a semiconductor device according to claim 1 , wherein the first substrate is formed of a semiconductor material.

10. The method for manufacturing a semiconductor device according to claim 9 , wherein the first substrate is formed of a silicon material.

11. The method for manufacturing a semiconductor device according to claim 1 , wherein before the first substrate is removed, the first substrate has an insulating film contacting the support substrate.

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the insulating film is formed of silicon oxide.

13. The method for manufacturing a semiconductor device according to claim 1 , wherein the support substrate has a higher rigidity in one direction of the first principal surface than in another direction of the first principal surface.

14. The method for manufacturing a semiconductor device according to claim 1 , wherein the removing the first substrate is performed by polishing or etching.

Assignees

• Kioxia Corp

Inventors

• Ashidate Hiroaki
• Takeishi Tomoyuki

Classifications

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/941

  Dispositions of bond pads · CPC title

• H10W80/163

  using active alignment, e.g. detecting marks and correcting position · CPC title

• H10W80/211

  using auxiliary members, e.g. aids for protecting the bonding area · CPC title

• H10W90/00

  Package configurations · CPC title