Semiconductor device, display apparatus, and electronic device

Patent metadata

Field	Value
Publication number	US-12400605-B2
Application number	US-202218560716-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	May 27, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

First claim

The invention claimed is:

1. A semiconductor device comprising a circuit, the circuit comprising:
a first driver circuit comprising a first signal generation circuit and a first switch;
a second driver circuit comprising a second signal generation circuit and a second switch;
a switch circuit comprising a third switch;
a first selection circuit comprising a fourth switch and a fifth switch;
a second selection circuit comprising a sixth switch and a seventh switch;
a first terminal of the circuit;
a second terminal of the circuit;
a third terminal of the circuit; and
a fourth terminal of the circuit,
wherein a potential of a fifth terminal is input to the first driver circuit through a first inverter,
wherein a potential of a sixth terminal is input to the second driver circuit through a second inverter,
wherein the potential of the fifth terminal and the potential of the sixth terminal is input to an XOR circuit,
wherein a potential output from the XOR circuit is input to a control terminal of the third switch,
wherein the first signal generation circuit is configured to generate a first data signal,
wherein the second signal generation circuit is configured to generate a second data signal,
wherein the first signal generation circuit is electrically connected to a first terminal of the first switch,
wherein a second terminal of the first switch is electrically connected to a first terminal of the third switch, a first terminal of the fourth switch, and a first terminal of the fifth switch,
wherein the second signal generation circuit is electrically connected to a first terminal of the second switch,
wherein a second terminal of the second switch is electrically connected to a second terminal of the third switch, a first terminal of the sixth switch, and a first terminal of the seventh switch,
wherein a second terminal of the fourth switch is electrically connected to the first terminal of the circuit,
wherein a second terminal of the fifth switch is electrically connected to the second terminal of the circuit,
wherein a second terminal of the sixth switch is electrically connected to the third terminal of the circuit, and
wherein a second terminal of the seventh switch is electrically connected to the fourth terminal of the circuit.

2. The semiconductor device according to claim 1 ,
wherein the first switch, the second switch, and the third switch are each an analog switch.

3. A display apparatus comprising:
the semiconductor device according to claim 1 ; and
a first pixel circuit capable of being electrically connected to the first terminal and the second terminal of the circuit,
wherein, when the first pixel circuit is electrically connected to one of the first terminal and the second terminal of the circuit, the first pixel circuit is not electrically connected to the other of the first terminal and the second terminal of the circuit.

4. A display apparatus comprising:
the semiconductor device according to claim 1 ;
a first pixel circuit electrically connected to the first terminal of the circuit; and
a second pixel circuit electrically connected to the second terminal of the circuit.

Assignees

• Semiconductor Energy Lab

Inventors

• Kozuma Munehiro
• Onuki tatsuya
• Matsuzaki Takanori
• Ito Minato

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title