Display system and shared driving circuit thereof

Patent metadata

Field	Value
Publication number	US-11132939-B2
Application number	US-202016822584-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Mar 28, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A display system includes a number (M) of scan line units, a number (N) of channel line units, a number (R) of light emitting arrays connected to the scan line units and the channel line units, and a number (L) of shared driving circuits, where M≥1, N≥1, R≥1, and L is equal to a maximum of M and N when M≠N, and is equal to M otherwise. Each shared driving circuit is operable to generate or not to generate a scan driving output, and is operable to generate or not to generate a channel driving output. Each of a number (M) of the shared driving circuits is for providing the scan driving output to a respective scan line unit. Each of a number (N) of the shared driving circuits is for providing the scan driving output to a respective scan line unit.

First claim

What is claimed is:

1. A display system comprising:
a number (M) of scan line units, where M>1;
a number (N) of channel line units, where N>1;
a number (R) of light emitting arrays, where R≥1; and
a number (L) of shared driving circuits, where L is equal to a maximum of M and N when W≠N, and is equal to M otherwise;
each of said light emitting arrays is connected to a corresponding one of said scan line units and a corresponding one of said channel line units;
each of said shared driving circuits including
a control circuit for receiving an enable control output, and generating a scan enable signal and a channel enable signal based on the enable control output, a scan driver connected to said control circuit for receiving the scan enable signal therefrom, and operable to generate or not to generate a scan driving output based on the scan enable signal, and
a channel driver connected to said control circuit for receiving the channel enable signal therefrom, and operable to generate or not to generate a channel driving output based on the channel enable signal;

said scan driver of each of a number (M) of said shared driving circuits being further connected to a respective one of said scan line units for providing the scan driving output thereto;
said channel driver of each of a number (N) of said shared driving circuits being further connected to a respective one of said channel line units for providing the channel driving output thereto; and
one of said light emitting arrays being connected to said scan driver of one of said shared driving circuits via the corresponding one of said scan line units, and being connected to said channel driver of another one of said shared driving circuits via the corresponding one of said channel line units.

2. The display system of claim 1 , wherein each of said shared driving circuits further includes:
a clock generator for receiving a reference clock signal, and generating an internal global clock signal based on the reference clock signal; and
a signal processor connected to said clock generator for receiving the internal global clock signal therefrom, for further receiving display data, providing the enable control output, and generating a scan control output and a channel control output based on the internal global clock signal and the display data;
said control circuit being further connected to said signal processor for receiving the enable control output therefrom;
said scan driver being further connected to said signal processor for receiving the scan control output therefrom, and generating the scan driving output based on the scan control output;
said channel driver being further connected to said signal processor for receiving the channel control output therefrom, and generating the channel driving output based on the channel control output.

3. The display system of claim 2 , wherein said clock generator is a delay-locked loop.

4. The display system of claim 2 , wherein said clock generator is a phase-locked loop.

5. The display system of claim 2 , wherein for each of said shared driving circuits:
the scan driving output includes a plurality of scan driving signals;
the scan control output includes a scan clock signal and a scan control setting; and
said scan driver includes
a scan controller connected to said control circuit for receiving the scan enable signal therefrom, further connected to said signal processor for receiving the scan control output therefrom, and generating a plurality of scan control signals, which respectively correspond to the scan driving signals, based on the scan enable signal and the scan control output, and
a plurality of scan switches each having a first terminal that is for providing a respective one of the scan driving signals, a second terminal that is adapted to be connected to a power rail, and a control terminal that is connected to said scan controller for receiving therefrom one of the scan control signals which corresponds to the respective one of the scan driving signals; and

the scan driving signals are generated by said scan controller in such a way that
when the scan enable signal is in an active state, at least some of said scan switches transition between conduction and non-conduction in synchrony with the scan clock signal, and a number of the at least some of said scan switches is related to the scan control setting, and
when the scan enable signal is in an inactive state, none of said scan switches conducts.

6. The display system of claim 5 , wherein for each of said shared driving circuits, said scan driver further includes:
a plurality of amplifiers, each of which is connected to said first terminal of a respective one of said scan switches, each of which is further connected to said scan controller for receiving therefrom one of the scan control signals that is received by the respective one of said scan switches, and each of which adjusts a magnitude of a voltage at said first terminal of the respective one of said scan switches to a predetermined reference voltage value when the one of the scan control signals causes the respective one of said scan switches to not conduct.

7. The display system of claim 5 , wherein for each of said shared driving circuits, each of said scan switches is an N-type power semiconductor transistor, and is for receiving a ground voltage from the power rail.

8. The display system of claim 5 , wherein for each of said shared driving circuits, each of said scan switches is a P-type power semiconductor transistor, and is for receiving, from the power rail, a supply voltage with a magnitude that falls within a range of 3.2V to 5V.

9. The display system of claim 2 , wherein for each of said shared driving circuits:
the channel driving output includes a plurality of driving current signals;
the channel control output includes a current gain control setting, a reference voltage control setting, and a plurality of pulse width modulation (PWM) signals which respectively correspond to the driving current signals and each of which has a pulse width related to the display data;
said channel driver includes
a control generator connected to said control circuit for receiving the channel enable signal therefrom, further connected to said signal processor for receiving the PWM signals therefrom, and generating a plurality of channel control signals, which respectively correspond to the driving current signals, based on the channel enable signal and the PWM signals,
a current gain controller connected to said signal processor for receiving the current gain control setting therefrom, and generating a current gain control output based on the current gain control setting,
a current provider connected to said current gain controller for receiving the current gain control output therefrom, providing a plurality of driving currents, and adjusts magnitudes of the driving currents based on the current gain control output,
a plurality of channel switches each having a first terminal that is connected to said current provider, a second terminal that is for providing a respective one of the driving current signals, and a control terminal that is connected to said control generator for receiving therefrom one of the channel control signals which corresponds to the respective one of the driving current signals, each of said channel switches permitting a respective one of the driving currents to flow therethrough when conducting, and
an amplifier unit connected to said second terminals of said channel switches, further connected to said signal processor for receiving the reference voltage control setting therefrom, and further connected to said control generator for receiving the channel control signals there

Assignees

• Macroblock Inc

Inventors

• Yen Hung-Lin
• Hsieh Shun-Ching

Classifications

• G09G3/3633

  with transmission/voltage characteristic comprising multiple loops, e.g. antiferroelectric liquid crystals · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title