Data protection for three-dimensional NAND memory

Patent metadata

Field	Value
Publication number	US-12399643-B2
Application number	US-202117487870-A
Country	US
Kind code	B2
Filing date	Sep 28, 2021
Priority date	Jun 30, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

The present disclosure provides a method of data protection for a three-dimensional NAND memory. The method includes programming a memory cell of the 3D NAND memory according to programming data; and backing up a portion of the programming data associated with the memory cell in response to a program loop count (PLC) that is larger than a threshold value, where the PLC tracks a repeated number of the programming of the memory cell. A previous PLC can be set as the threshold value, where the previous PLC was used by a previous programming operation and was collected after the memory cell was programmed successfully to a previous target logic state.

First claim

What is claimed is:

1. A method of data protection for a three-dimensional (3D) NAND memory, comprising:
programming a memory cell of the 3D NAND memory according to programming data;
in response to programming the memory cell according to the programming data, verifying whether the memory cell is at a target logic state according to the programming data;
determining a program loop count (PLC) of the memory cell;
in response to the PLC being greater than a threshold value, designating the memory cell as risky;
programming the memory cell according to second programming data;
in response to programming the memory cell according to the second programming data, verifying whether the memory cell is at the target logic state according to the second programming data; and
in response to verifying that the memory cell is at the target logic state and the memory cell being designated as risky, backing up a portion of the second programming data.

2. The method of claim 1 , further comprising:
after programming the memory cell, verifying whether the memory cell is at a target logic state according to the programming data; and
repeating the programming of the memory cell when the memory cell is not at the target logic state.

3. The method of claim 2 , further comprising:
collecting the PLC that tracks a repeated number of the programming.

4. The method of claim 1 , further comprising:
prior to programming the memory cell, backing up the portion of the programming data associated with the memory cell in response to a previous risky marking of the memory cell from a previous programming operation.

5. The method of claim 1 , wherein the backing up the portion of the programming data associated with the memory cell comprises programming a redundant memory cell with the portion of the programming data associated with the memory cell.

6. The method of claim 5 , further comprising:
recovering the portion of the programming data associated with the memory cell from the redundant memory cell in response to an unrecoverable error correction code.

7. The method of claim 1 , further comprising:
setting a previous PLC as the threshold value, wherein the previous PLC was used by a previous programming operation and was collected after the memory cell was programmed successfully to a previous target logic state.

8. The method of claim 1 , wherein the programming the memory cell comprises:
programming the memory cell simultaneously with other memory cells in a memory page, wherein all memory cells in the memory page share a word line.

9. The method of claim 8 , further comprising:
backing up portions of the programming data associated with the memory page in response to the PLC of the memory cell.

10. The method of claim 9 , wherein the backing up the portions of the programming data associated with the memory page comprises programming a redundant memory page with the portions of the programming data associated with the memory page.

11. The method of claim 10 , further comprising:
recovering the portions of the programming data associated with the memory page from the redundant memory page in response to an unrecoverable error correction code.

12. A memory storage system, comprising:
a three-dimensional (3D) NAND memory, comprising:
a plurality of memory strings, penetrating through a film stack of alternating conductive and dielectric layers disposed on a substrate, wherein each memory string comprises a plurality of memory cells; and
a memory controller, configured to:
send programming data to the 3D NAND memory to program a memory cell;
in response to programming the memory cell according to the programming data, verify whether the memory cell is at a target logic state according to the programming data;
determine a program loop count (PLC) of the memory cell;
in response to the PLC being greater than a threshold value, mark the memory cell as risky:
program the memory cell according to second programming data;
in response to programming the memory cell according to the second programming data, verify whether the memory cell is at the target logic state according to the second programming data; and
in response to verifying that the memory cell is at the target logic state and the memory cell being marked as risky, back up a portion of the second programming data.

13. The memory storage system of claim 12 , wherein the PLC tracks a number of programming for the memory cell to reach a target logic state according to the programming data.

14. The memory storage system of claim 12 , wherein the memory controller is further configured to create a risky block table for the 3D NAND memory, wherein the risky block table comprises a first set of addresses identifying the memory cell marked risky.

15. The memory storage system of claim 14 , wherein the memory controller is further configured to create a risky to backup table for the 3D NAND memory, wherein the risky to backup table comprises:
the first set of addresses identifying the memory cell marked risky; and
a second set of addresses identifying a redundant memory cell, wherein the redundant memory cell is programmed with the portion of the programming data associated with the memory cell marked risky.

16. The memory storage system of claim 15 , wherein the memory controller is further configured to recover the portion of programming data associated with the memory cell from the redundant memory cell when an unrecoverable error correction code is received.

17. The memory storage system of claim 12 , wherein the threshold value is a previous PLC used by a previous programming operation and was collected after the memory cell was programmed successfully to a previous target logic state.

18. The memory storage system of claim 12 , wherein the memory controller is further configured to back up the portion of the programming data associated with the memory cell, in response to a previous risky marking of the memory cell from a previous programming operation, before the memory cell is programmed.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wan Jie
• Tao Wei
• Tao Yuan
• Du Ling
• Cheng Boxuan
• Cao Jian

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title