Apparatus and method for monitoring a semiconductor component
US-2024019482-A1 · Jan 18, 2024 · US
US12396366B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12396366-B2 |
| Application number | US-202017612677-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 23, 2020 |
| Priority date | Jul 5, 2019 |
| Publication date | Aug 19, 2025 |
| Grant date | Aug 19, 2025 |
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A semiconductor component that includes at least one dielectric layer and at least one first electrode and one second electrode. In addition, at least two defect types different from one another are present in the dielectric layer. These at least two defect types different from one another move along localized defect states, each at an average effective distance, in the direction of one of the two electrodes as a function of an operating voltage that is applied between the first electrode and the second electrode, and an operating temperature that is present. The average effective distance is greater than 3.2 nm.
Opening claim text (preview).
What is claimed is: 1. A semiconductor component, comprising: at least one dielectric layer; and at least one first electrode and one second electrode; wherein at least two defect types different from one another being present in the dielectric layer, the at least two different defect types moving along localized defect states, each case having the same average effective distance a 0 , in a direction of one of the first and second electrodes, as a function of an operating voltage applied between the first electrode and the second electrode, and an operating temperature that is present, and a 0 >3.2 nm. 2. The semiconductor component as recited in claim 1 , wherein a 0 >3.24 nm. 3. The semiconductor component as recited in claim 1 , wherein at least three defect types different from one another are present in the dielectric layer. 4. The semiconductor component as recited in claim 1 , wherein the dielectric layer is a polycrystalline oxidic high-k dielectric, wherein the dielectric layer is selected from a PZT layer or a KNN layer. 5. The semiconductor component as recited in claim 4 , wherein the dielectric layer is a sputtered PZT layer. 6. The semiconductor component as recited in claim 5 , wherein the sputtered PZT layer has a deposition temperature of less than 500° C. 7. The semiconductor component as recited in claim 5 , wherein the sputtered PZT layer has a composition of Pb 1.3 (Zr 0.52 Ti 0.48 )O 3 .
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