Stacked 2D CMOS with inter metal layers

Patent metadata

Field	Value
Publication number	US-12396254-B2
Application number	US-202117485225-A
Country	US
Kind code	B2
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first transistor on a first level;
a second transistor on a second level above the first level;
an insulating layer between the first level and the second level; and
a via through the insulating layer, wherein the via electrically couples the first transistor to the second transistor, wherein each of the first transistor and the second transistor comprises:
a first channel;
a second channel over the first channel;
a gate structure between the first channel and the second channel;
a source contact on a first end of the first channel and the second channel; and
a drain contact on a second end of the first channel and the second channel.

2. The semiconductor device of claim 1 , wherein the first transistor further comprises:
a first spacer between the source contact and the gate structure; and
a second spacer between the drain contact and the gate structure.

3. The semiconductor device of claim 1 , wherein the source contact and the drain contact wrap around ends of the first channel and ends of the second channel.

4. The semiconductor device of claim 1 , wherein the source contact and the drain contact comprise a conformal layer and a fill layer.

5. The semiconductor device of claim 4 , wherein the conformal layer comprises antimony and the fill layer comprises gold.

6. The semiconductor device of claim 1 , wherein the via electrically couples the source contact of the first transistor to the source contact of the second transistor.

7. The semiconductor device of claim 1 , wherein the first transistor is a P-type transistor, and wherein the second transistor is an N-type transistor.

8. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are components of an SRAM cell.

9. The semiconductor device of claim 8 , wherein the first transistor and the second transistor are components of a six transistor (6T) SRAM cell.

10. The semiconductor device of claim 1 , wherein the first transistor and the second transistor are gate-all-around (GAA) transistors.

11. An SRAM cell comprising:
a first transistor in a first layer;
a second transistor in the first layer;
a third transistor in a second layer;
a fourth transistor in the second layer;
a fifth transistor in the second layer;
a sixth transistor in the second layer;
an insulating layer between the first layer and the second layer; and
vias through the insulating layer, wherein the vias electrically couple the first transistor and the second transistor to the fourth transistor and the fifth transistor, wherein each of the first, second, third, fourth, fifth and sixth transistors comprises:
a first channel;
a second channel over the first channel;
a gate structure between the first channel and the second channel;
a source contact on a first end of the first channel and the second channel; and
a drain contact on a second end of the first channel and the second channel.

12. The SRAM cell of claim 11 , wherein the first transistor and the second transistor are P-type transistors, and wherein the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors.

13. The SRAM cell of claim 11 , wherein each of the first transistor and the second transistor further comprises:
a first spacer between the source contact and the gate structure; and
a second spacer between the drain contact and the gate structure.

14. The SRAM cell of claim 11 , wherein the source contact and the drain contact wrap around ends of the first channel and ends of the second channel.

15. The SRAM cell of claim 14 , wherein the source contact and the drain contact comprise a conformal layer and a fill layer.

16. The SRAM cell of claim 15 , wherein the conformal layer comprises antimony and the fill layer comprises gold.

17. An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises:
a first transistor on a first level;
a second transistor on a second level above the first level;
an insulating layer between the first level and the second level; and
a via through the insulating layer, wherein the via electrically couples the first transistor to the second transistor, wherein each of the first transistor and the second transistor comprises:
a first channel;
a second channel over the first channel;
a gate structure between the first channel and the second channel;
a source contact on a first end of the first channel and the second channel; and
a drain contact on a second end of the first channel and the second channel.

18. The electronic system of claim 17 , wherein the first transistor and the second transistor are part of a six transistor SRAM cell.

19. The electronic system of claim 17 , wherein each of the first transistor further comprises:
a first spacer between the source contact and the gate structure; and
a second spacer between the drain contact and the gate structure.

Assignees

• Intel Corp

Inventors

• O'Brien Kevin P
• Avci Uygar E
• Clendenning Scott B
• Dorow Chelsey
• Lee Sudarat
• Maxey Kirby
• Naylor Carl H
• Tronic Tristan A
• Shivaraman Shriram
• Penumatcha Ashish Verma

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title