Semiconductor devices including resistor structures

Patent metadata

Field	Value
Publication number	US-12396184-B2
Application number	US-202318371328-A
Country	US
Kind code	B2
Filing date	Sep 21, 2023
Priority date	Jun 26, 2017
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a resistor structure including a first insulating layer on a substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and
forming a resistor contact hole penetrating the second insulating layer and the resistor layer; and
forming a resistor contact filling the resistor contact hole, the resistor contact directly contacting the first insulating layer,
wherein a tilt angle of a side wall of the resistor contact with respect to a vertical direction perpendicular to an upper surface of the substrate varies according to a height from the substrate,
wherein the tilt angle is an oblique angle relative to the vertical direction, and
wherein a width of an upper end of the resistor contact is larger than a width of a lower end of the resistor contact.

2. The method as claimed in claim 1 , wherein the forming the resistor contact hole includes:
performing a first etching process to pattern the second insulating layer; and
performing a second etching process of etching the resistor layer using the second insulating layer as an etch mask.

3. The method as claimed in claim 2 , wherein the second etching process is performed by using an etching material having a low chemical reactivity with a material that constitutes the resistor layer.

4. The method as claimed in claim 3 , wherein, in the second etching process, the resistor layer is etched by physical collision with the etching material.

5. The method as claimed in claim 4 , wherein, in the second etching process, particles constituting the resistor layer are separated from a lower portion of the resistor contact hole by physical collision, and deposited on a side wall of the resistor contact hole.

6. The method as claimed in claim 5 , wherein, in the second etching process, a tilt angle of a side wall of the resistor contact hole with respect to the vertical direction is changed where the resistor contact hole contacts the resistor layer.

7. The method as claimed in claim 3 , wherein in the second etching process, the first insulating layer is etched using the resistor layer as an etch mask.

8. The method as claimed in claim 7 , wherein, in the second etching process, the tilt angle of the side wall of the resistor contact hole with respect to the vertical direction is changed where the resistor contact hole contacts the first insulating layer.

9. The method as claimed in claim 7 , wherein the second etching process is performed until a lower portion of the resistor contact hole exposes the first insulating layer.

10. The method as claimed in claim 7 , wherein the second etching process is performed until a bottom surface of the resistor contact is disposed lower than a bottom surface of the resistor structure.

11. A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate including a first region and a second region;
forming an active region disposed on the first region and the second region of the substrate;
forming a lower structure on the first region and the second region of the substrate, the lower structure including a gate structure and a lower interlayer insulating layer that contacts a side wall of the gate structure;
forming a resistor structure on the lower structure on the second region of the substrate, the resistor structure including a first insulating layer, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer;
forming a resistor contact hole penetrating the second insulating layer and the resistor layer; and
forming a resistor contact filling the resistor contact hole, the resistor contact directly contacts the first insulating layer,
wherein the forming the resistor contact hole includes:
performing a first etching process to pattern the second insulating layer and the first insulating layer; and
performing a second etching process of etching the resistor layer using the second insulating layer as an etch mask and the first insulating layer using the resistor layer as an etch mask, and

wherein in the second etching process, a tilt angle of a side wall of the resistor contact hole with respect to a vertical direction perpendicular to an upper surface of the substrate is changed where the resistor contact hole penetrates the resistor layer and where the resistor contact hole penetrates the first insulating layer.

12. The method as claimed in claim 11 ,
wherein the second etching process is performed by using an etching material having a low chemical reactivity with a material that constitutes the resistor layer, and
wherein, in the second etching process, the resistor layer is etched by physical collision with the etching material.

13. The method as claimed in claim 12 , wherein, in the second etching process, particles constituting the resistor layer are separated from a lower portion of the resistor contact hole by physical collision, and deposited on a side wall of the resistor contact hole.

14. The method as claimed in claim 11 , wherein the tilt angle of the side wall of the resistor contact with respect to the vertical direction changes at a first height from the substrate and a second height, greater than the first height.

15. The method as claimed in claim 11 ,
wherein the resistor contact comprises a first region having a side wall that has a first tilt angle with respect to the vertical direction, a second region located on the first region and having a side wall that has a second tilt angle with respect to the vertical direction, and a third region located on the second region and having a side wall that has a third tilt angle with respect to the vertical direction; and
wherein the first tilt angle is less than the second tilt angle, and the second tilt angle is greater than the third tilt angle.

16. The method as claimed in claim 11 , further comprising:
forming a source/drain region under the side wall of the gate structure on the first region of the substrate; and
forming a source/drain contact contacting the source/drain region on the first region of the substrate.

17. The method as claimed in claim 16 , wherein a tilt angle of a side wall of the source/drain contact with respect to the vertical direction is constant regardless of a height from the substrate.

18. A method of manufacturing a semiconductor device, the method comprising:
preparing a substrate including a first region and a second region;
forming an active region disposed on the first region and the second region of the substrate;
forming a lower structure on the first region and the second region of the substrate, the lower structure including a gate structure and a lower interlayer insulating layer that contacts a side wall of the gate structure;
forming a source/drain region under the side wall of the gate structure on the first region of the substrate;
forming a resistor structure on the lower structure on the second region of the substrate, the resistor structure including a first insulating layer, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer;
forming a resistor contact hole penetrating the second insulating layer and the resistor layer;
forming a resistor contact filling the resistor contact hole, the resistor contact directly contacts the first insulating layer; and
forming a source/drain contact contacting the source/drain region on the first region of the substrate,
wherein the resi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Tae-Yeol
• Ra Hyon-Wook
• Lee Seo-Bum
• Kim Jun-Soo
• Shin Chung-Hwan

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title