Method of fabricating semiconductor device having a resistor structure

Patent metadata

Field	Value
Publication number	US-9406770-B2
Application number	US-201514668430-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Jul 16, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a substrate including a transistor area and a resistor area;
forming active gate structures on the substrate in the transistor area;
forming dummy gate structures on the substrate in the resistor area;
forming a lower interlayer insulating layer on the substrate to cover side walls of the active gate structures and the dummy gate structures;
forming a resistor structure comprising a buffer insulating pattern, a resistor element, and an etch-retard pattern stacked sequentially on the dummy gate structures and the lower interlayer insulating layer in the resistor area;
forming an intermediate interlayer insulating layer on the lower interlayer insulating layer to cover the resistor structure;
forming resistor contact structures configured to pass through the intermediate interlayer insulating layer and the etch-retard pattern, and to contact the resistor element; and
forming an upper interlayer insulating layer on the intermediate interlayer insulating layer and the resistor contact structures.

2. The method according to claim 1 , further comprising forming source/drain areas in the substrate between the active gate structures,
wherein the source/drain areas are covered by the lower interlayer insulating layer.

3. The method according to claim 2 , further comprising forming gate contact structures configured to pass through the intermediate interlayer insulating layer in the transistor area, and source/drain contact structures configured to pass through the intermediate interlayer insulating layer and the lower interlayer insulating layer, and
forming the upper interlayer insulating layer on the intermediate interlayer insulating layer to cover the source/drain contact structures and the gate contact structures,
wherein the source/drain contact structures are in contact with the source/drain areas, and the gate contact structures are in contact with the active gate structures.

4. The method according to claim 3 , wherein the forming of each of the gate contact structures comprises:
forming a core pattern including tungsten;
forming a barrier pattern including a metallic nitride which covers a lower surface and side surfaces of the core pattern; and
forming a glue pattern including a metallic material disposed under the barrier pattern and in contact with each of the active gate structures.

5. The method according to claim 3 , wherein the forming of each of the source/drain contact structures comprises:
forming a core pattern including tungsten;
forming a barrier pattern including a metallic nitride which covers a lower surface and side surfaces of the core pattern; and
forming a silicide pattern disposed under the barrier pattern and in contact with each of the source/drain areas.

6. The method according to claim 1 , wherein a side surface of the buffer insulating pattern, a side surface of the resistor element, and a side surface of the etch-retard pattern are substantially vertically aligned.

7. The method according to claim 1 , wherein the resistor contact structures extend into the resistor element.

8. The method according to claim 1 , wherein the forming of each of the resistor contact structures comprises:
forming a core pattern including tungsten;
forming a barrier pattern including a metallic nitride which covers a lower surface and side surfaces of the core pattern; and
forming a silicide pattern disposed under the barrier pattern and in contact with the resistor element.

9. The method according to claim 1 , wherein the resistor element includes tungsten silicide.

10. The method according to claim 1 , wherein the etch-retard pattern includes silicon nitride.

11. A method of fabricating a semiconductor device, comprising:
providing a substrate including a transistor area and a resistor area;
forming active gate structures on the substrate in the transistor area, and dummy gate structures on the substrate in the resistor area;
forming source/drain areas in the substrate between the active gate structures;
forming a lower interlayer insulating layer on the substrate between the active gate structures and between the dummy gate structures to cover the source/drain areas;
sequentially forming a buffer insulating layer, a resistor conductive layer, and an etch-retard layer on the active gate structures, the dummy gate structures, and the lower interlayer insulating layer;
patterning the buffer insulating layer, the resistor conductive layer, and the etch-retard layer, and forming a resistor structure including a buffer insulating pattern, a resistor element, and an etch-retard pattern in the resistor area, wherein a side surface of the buffer insulating pattern, a side surface of the resistor element, and a side surface of the etch-retard pattern are substantially and vertically arranged;
forming an intermediate interlayer insulating layer configured to cover the active gate structures, the dummy gate structures, the lower interlayer insulating layer, and the resistor structures;
forming first contact holes configured to expose the source/drain areas in the intermediate interlayer insulating layer and the lower interlayer insulating layer, second contact holes configured to expose the resistor element in the intermediate interlayer insulating layer and the etch-retard pattern, and third contact holes configured to expose the active gate structures in the intermediate interlayer insulating layer;
forming source/drain contact structures in the first contact holes, resistor contact structures in the second contact holes, and gate contact structures in the third contact holes; and
forming an upper interlayer insulating layer on the intermediate interlayer insulating layer to cover the source/drain contact structures, the resistor contact structures, and the gate contact structures.

12. The method according to claim 11 , wherein the first contact holes, the second contact holes, and the third contact holes are formed at a same time.

13. The method according to claim 11 , wherein the forming of the source/drain contact structures, the resistor contact structures, and the gate contact structures comprises:
forming a silicide pattern in each of the first contact holes and the second contact holes, and forming a conductive pattern in the third contact holes;
forming a barrier layer on inside walls of the first to third contact holes;
forming a metallic material layer on the barrier layer to fill the first to third contact holes; and
planarizing the barrier layer and the metallic material layer, and forming a barrier pattern and a metallic pattern in each of the first to third contact holes.

14. The method according to claim 13 , wherein the forming of the silicide pattern comprises:
forming the conductive pattern in the first contact holes and the second contact holes; and
silicidizing the conductive pattern by a heat treatment.

15. The method according to claim 11 , wherein the lower interlayer insulating layer includes silicon oxide, and the buffer insulating pattern includes silicon oxide which is denser than the lower interlayer insulating layer.

16. A method, comprising:
providing a substrate comprising a transistor area and a resistor area;
forming gate structures on the resistor area of the substrate;
forming a resistor element of on the gate structures;
forming an etch-retard pattern on the resistor element, the etch-retard pattern having openings formed therein to expose the resistor element; and
forming resistor contact structures comprising a si

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Hyun-Seung
• Jun Hwi-Chan

Classifications

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title