Technologies for accelerated QUIC packet processing with hardware offloads

Patent metadata

Field	Value
Publication number	US-12395474-B2
Application number	US-202318514713-A
Country	US
Kind code	B2
Filing date	Nov 20, 2023
Priority date	Mar 16, 2018
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. One or more non-transitory computer-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause one or more processors to:
configure circuitry of a network interface controller to perform segmentation of a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet to generate payload segments, to perform encryption of the payload segments, to generate a QUIC header for an encrypted payload segment of the encrypted payload segments based on a copy of a QUIC header of the QUIC packet, and cause transmission of packets with generated QUIC headers and encrypted QUIC payload segments and
configure a second circuitry of the network interface controller to decrypt a received encrypted QUIC payload segment, perform receive side scaling (RSS) to identify a core to process the received decrypted QUIC payload segment, and copy the decrypted payload segment to a queue associated with the identified core.

2. The one or more computer-readable storage media of claim 1 , wherein the QUIC packet comprises a UDP packet that includes the QUIC header and the payload, and wherein the QUIC packet is associated with a QUIC connection.

3. The one or more computer-readable storage media of claim 1 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the one or more processors to:
program the network interface controller with an encryption key associated with a QUIC connection, wherein the QUIC packet is associated with the QUIC connection.

4. The one or more computer-readable storage media of claim 3 , wherein the circuitry is to perform encryption of the payload segments based on the encryption key.

5. The one or more computer-readable storage media of claim 3 , wherein the circuitry is to perform encryption of the payload segments based on an application-layer encryption protocol.

6. The one or more computer-readable storage media of claim 1 , further comprising a plurality of instructions stored thereon that, in response to being executed, cause the one or more processors to:
program the network interface controller to:
update a packet number of the copy of the QUIC header of at least one of the packets with the encrypted QUIC payload segments to differentiate packets with different encrypted QUIC payload segments.

7. An apparatus comprising:
an interface and
a network interface controller coupled to the interface, the network interface controller comprising:
a direct memory access (DMA) circuitry;
a host interface;
a network interface;
circuitry to segment a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet, to generate payload segments, and to perform encryption of the payload segments prior to transmission of the QUIC payload segments; and
second circuitry to decrypt an encrypted QUIC payload received from a sender network interface device, perform receive side scaling (RSS) to identify a core to process the received decrypted QUIC payload, and copy the decrypted payload to a queue associated with the identified core.

8. The apparatus of claim 7 , wherein the QUIC packet comprises a UDP packet that includes a QUIC header and the payload, and wherein the QUIC packet is associated with a QUIC connection.

9. The apparatus of claim 7 , wherein the circuitry is to encrypt the payload segments based on an encryption key associated with a QUIC connection, wherein the QUIC packet is associated with a QUIC connection.

10. The apparatus of claim 7 , wherein the circuitry is to encrypt the payload segments based on an encryption key associated with a QUIC connection, wherein the circuitry is to perform encryption of the payload segments based on an application-layer encryption protocol.

11. The apparatus of claim 7 , wherein to segment the QUIC packet to generate payload segments comprises:
update a packet number of the copy of a QUIC header of the encrypted QUIC payload segments to differentiate packets with different encrypted QUIC payload segments.

12. A method comprising:
a network interface controller comprising: a host interface, direct memory access (DMA) circuitry, and host interface performing:
segmenting a payload of a Quick User Datagram Protocol (UDP) Internet Connection (QUIC) packet into a plurality of payload segments;
performing encryption of the payload segments;
generating segmented QUIC packets with the encrypted payload segments with QUIC packet headers based on a copy of a QUIC header of the QUIC packet, wherein the QUIC packet headers for different segmented QUIC packets include packet numbers that differentiate different encrypted payload segments;
transmitting the segmented QUIC packets with encrypted payloads; and
decrypting a received encrypted QUIC payload segment and performing receive side scaling (RSS) to determine a queue associated with a processor of a plurality of processors for the processor to process the received decrypted QUIC payload segment.

13. The method of claim 12 , wherein the encrypting the payload segments comprises encrypting the payload segments based on an encryption key associated with a QUIC connection and based on an application-layer encryption protocol.

14. The method of claim 12 , wherein the generating segmented QUIC packets with the encrypted payload segments with QUIC packet headers based on a copy of a QUIC header of the QUIC packet comprises updating a packet number of the copy of the QUIC header for the segmented QUIC packets.

Assignees

• Intel Corp

Inventors

• Deval Manasi
• Bowers Gregory

Classifications

• H04L69/164

  Adaptation or special uses of UDP protocol · CPC title

• H04L63/06

  for supporting key management in a packet data network (cryptographic mechanisms or cryptographic arrangements for key management H04L9/08) · CPC title

• H04L69/321

  Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers · CPC title

• H04L69/161

  Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields · CPC title

• H04L69/324

  in the data link layer [OSI layer 2], e.g. HDLC · CPC title