High-efficiency amplifier architecture with de-gain stage

Patent metadata

Field	Value
Publication number	US-12395136-B2
Application number	US-202217853945-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Sep 10, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

First claim

What is claimed is:

1. An amplifier, comprising:
an input stage, configured to receive an input signal to generate an amplified signal;
an amplifier stage, coupled to the input stage, configured to generate a first driving signal and a second driving signal according to the amplified signal;
a power stage comprising a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal; and
a de-gain stage, coupled to the power stage, configured to generate a first control signal to the first input terminal according to the second driving signal;
wherein the de-gain stage comprises:
a first low-pass filter, configured to filter the second driving signal to generate a filtered second driving signal; and
a first control circuit, coupled to the first low-pass filter, configured to generate the first control signal to the first input terminal of the power stage to limit a swing of the first driving signal according to the filtered second driving signal.

2. The amplifier of claim 1 , wherein the amplifier stage is a class-AB stage.

3. The amplifier of claim 1 , wherein in response to the filtered second driving signal being greater than a threshold level, the first control circuit couples the first input terminal of the power stage to the supply voltage or the output signal via a capacitor.

4. The amplifier of claim 3 , wherein in response to the filtered second driving signal not being greater than the threshold level, the first control circuit does not couple the first input terminal of the power stage to the supply voltage or the output signal via the capacitor.

5. The amplifier of claim 1 , wherein in response to the filtered second driving signal being greater than a threshold level, the first control circuit uses a transconductance amplifier to provide a current to the first input terminal of the power stage.

6. The amplifier of claim 5 , wherein in response to the filtered second driving signal not being greater than the threshold level, the first control circuit does not provide the current to the first input terminal of the power stage.

7. The amplifier of claim 5 , wherein the first control circuit comprises a damping circuit coupled between the first input terminal of the power stage and an internal terminal or an input terminal of the transconductance amplifier.

8. The amplifier of claim 1 , wherein the power stage further comprises a P-type transistor and an N-type transistor; and the P-type transistor is coupled between the supply voltage and an output terminal, the N-type transistor is coupled between the output terminal and the ground voltage, the P-type transistor receives the first driving signal from the first input terminal, and the N-type transistor receives the second driving signal from the second input terminal, to generate the output signal.

9. The amplifier of claim 8 , wherein the de-gain stage further comprises:
a second low-pass filter, configured to filter the first driving signal to generate a filtered first driving signal; and
a second control circuit, coupled to the second low-pass filter, configured to generate a second control signal to the second input terminal of the power stage to limit a swing of the second driving signal according to filtered first driving signal.

10. The amplifier of claim 9 , wherein in response to the filtered first driving signal being less than a threshold level, the second control circuit couples the second input terminal of the power stage to the ground voltage or the output signal via a capacitor.

11. The amplifier of claim 10 , wherein in response to the filtered first driving signal being not less than the threshold level, the second control circuit does not couple the second input terminal of the power stage to the ground voltage or the output signal via the capacitor.

12. The amplifier of claim 9 , wherein in response to the filtered first driving signal being less than a threshold level, the second control circuit uses a transconductance amplifier to provide a current to the second input terminal of the power stage.

13. The amplifier of claim 12 , wherein in response to the filtered first driving signal being not less than the threshold level, the second control circuit does not provide the current to the second input terminal of the power stage.

14. The amplifier of claim 1 , wherein the amplifier is a linear amplifier used in a supply modulator.

Assignees

• Mediatek Inc

Inventors

• Wen Sung-Han
• Lin Yu-Hung
• Chien Shih-Hsiung
• Chung Chi-Heng

Classifications

• H03F3/301

  CMOS common drain output SEPP amplifiers (H03F3/3008 takes precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2203/45708

  the LC comprising one SEPP circuit as output stage · CPC title

• H03F2203/45281

  One SEPP output stage being added to the differential amplifier · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title