System and method for reducing output harmonics

Patent metadata

Field	Value
Publication number	US-10461701-B2
Application number	US-201815875274-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jan 19, 2018
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.

First claim

What is claimed is:

1. A power amplifier system, comprising:
an amplification stage including a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output, and a second amplifier having an input coupled to said output of said first amplifier, a control input for receiving a second control signal, and an output;
a low-pass filter having a first input coupled to said output of said first amplifier, a second input coupled to said output of said second amplifier, and an output; and
a controller having a first input coupled to said output of said low-pass filter, a first output coupled to said control input of said first amplifier, and a second output coupled to said control input of said second amplifier, wherein said controller varies said first control signal to reduce a difference between said output of said low-pass filter and a first target voltage level, and varies said second control signal to reduce a difference between said output of said low-pass filter and a second target voltage level.

2. The power amplifier system of claim 1 , wherein said second target voltage level is different from said first target voltage level.

3. The power amplifier system of claim 1 , wherein:
said controller varies said first control signal to reduce said difference between said output of said low-pass filter and said first target voltage level during a coarse calibration period, and subsequently varies said second control signal to reduce said difference between said output of said low-pass filter and said second target voltage level during a fine calibration period.

4. The power amplifier system of claim 1 , wherein said first amplifier comprises:
a pullup path comprising:
a first set of inverters in which a pullup impedance of a first inverter and a pulldown impedance of a last inverter are controlled by a first trim signal;
a P-channel pullup transistor having a gate coupled to an output of said last inverter of said pullup path;

a pulldown path comprising:
a second set of inverters in which a pulldown impedance of a first inverter and a pullup impedance of a last inverter are controlled by a second trim signal; and
an N-channel pulldown transistor in series with said P-channel pullup transistor, wherein said first amplifier provides said output thereof at a common terminal between said P-channel pullup transistor and said N-channel pulldown transistor, said N-channel pulldown transistor having a gate coupled to an output of said last inverter of said pulldown path.

5. The power amplifier system of claim 1 , further comprising:
a non-overlap clock generator having an input coupled to said output of said first amplifier, and an output for providing a pullup signal and a pulldown signal having respective active states that are non-overlapping with respect to each other.

6. The power amplifier system of claim 5 , wherein:
said controller changes said first control signal in response to said output of said low-pass filter to make an average duty cycle of said pullup signal and said pulldown signal equal to approximately fifty percent.

7. The power amplifier system of claim 5 , wherein said second amplifier is a single-ended complementary amplifier stage comprising:
a first capacitor having a first terminal for receiving said pullup signal, and a second terminal;
a first resistor having a first terminal for receiving a first bias voltage, and a second terminal coupled to said second terminal of said first capacitor;
a second capacitor having a first terminal for receiving said pulldown signal, and a second terminal;
a second resistor having a first terminal for receiving a second bias voltage, and a second terminal coupled to said second terminal of said second capacitor;
a pullup drive transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode coupled to said second terminals of said first capacitor and said first resistor, and a second current electrode for providing said output of said amplification stage; and
a pulldown drive transistor having a first current electrode coupled to said second current electrode of said pullup drive transistor, a control electrode coupled to said second terminals of said second capacitor and said second resistor, and a second current electrode coupled to a second power supply voltage terminal.

8. The power amplifier system of claim 7 , wherein:
said first current electrode of said pullup drive transistor is coupled to said first power supply voltage terminal through a first bias transistor; and
said second current electrode of said pulldown drive transistor is coupled to said first power supply voltage terminal through a second bias transistor.

9. The power amplifier system of claim 1 , further comprising:
a single-ended to differential converter having an input coupled to said output of said first amplifier, and an output for providing true and complementary drive signals.

10. The power amplifier system of claim 9 , wherein said second amplifier comprises a differential complementary amplifier stage having first and second inputs for receiving said true and complementary drive signals, respectively, and first and second outputs for providing positive and negative output signals of a differential signal pair, respectively.

11. The power amplifier system of claim 9 , wherein said second amplifier comprises a differential open-drain amplifier stage having first and second inputs for receiving said true and complementary drive signals, respectively, and first and second outputs for providing positive and negative output signals of a differential open-drain signal pair, respectively, wherein said controller varies said second control signal to reduce a difference between said output of said low-pass filter and said second target voltage level.

12. The power amplifier system of claim 1 , wherein said second amplifier comprises a single-ended open-drain amplifier stage having an input coupled to said output of said first amplifier, and an output for providing an open-drain output signal to an integrated circuit terminal.

13. The power amplifier system of claim 12 , wherein said single-ended open-drain amplifier stage comprises:
a capacitor having a first terminal coupled to said output of said first amplifier, and a second terminal;
a resistor having a first terminal for receiving said second control signal, and a second terminal coupled to said second terminal of said capacitor;
a first transistor having a drain coupled to said integrated circuit terminal, a gate for receiving a bias signal, and a source; and
a second transistor having a drain coupled to said source of said first transistor, a gate coupled to said second terminals of said capacitor and said resistor, and a source coupled to a power supply voltage terminal.

14. A power amplifier system, comprising:
an amplification stage having an input for receiving an input signal, and an output coupled to an integrated circuit terminal, said amplification stage comprises a plurality of amplifiers connected in series, each amplifier having an input, a control input for receiving a respective control signal, and an output;
a low-pass filter having a first input coupled to outputs of each of said plurality of amplifiers, and an output; and
a controller having a first input coupled to said output of said low-pass filter, and outputs coupled to respective control inputs of each of said plurality of amplifiers, wherein said controller varies said respective control signal of each of said plurality of amplifiers to reduc

Assignees

• Silicon Lab Inc

Inventors

• Wu Sherry X
• Vasadi Sriharsha
• Koroglu Mustafa H
• Srinivasan Rangakrishnan

Classifications

• H03F2203/21157

  A filter circuit being added at the output of a power amplifier stage · CPC title

• H03F1/3205 Primary

  in field-effect transistor amplifiers · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title