Method for fabricating a semiconductor device package comprising a pin in the form of a drilling screw

US12394697B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12394697-B2
Application numberUS-202418442173-A
CountryUS
Kind codeB2
Filing dateFeb 15, 2024
Priority dateJul 3, 2020
Publication dateAug 19, 2025
Grant dateAug 19, 2025

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for fabricating a semiconductor device package, the method comprising: providing a die carrier; disposing at least one semiconductor die on the die carrier; electrically connecting an electrical connector with the semiconductor die or another electrical device; applying an encapsulation layer above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the metallic drilling screw contacts the electrical connector. 2. The method according to claim 1 , wherein screwing the metallic drilling screw comprises drilling the screw into the electrical connector. 3. The method of claim 1 , wherein the metallic drilling screw comprises a drilling end section, a screw section adjacent to the drilling end section, and a rod-shaped section adjacent to the screw section. 4. The method of claim 3 , wherein the metallic drilling screw further comprises a driver section, which is either located at an end of the rod-shaped section or integrated in an end of the rod-shaped section. 5. The method of claim 1 , wherein the metallic drilling screw is made by one of Cu, a Cu alloy, an Al alloy, or steel. 6. The method of claim 1 , wherein providing the die carrier comprises providing one out of a group consisting of a leadframe, a direct copper bonded substrate, a direct aluminum bonded substrate, and an active metal brazing substrate, wherein the die carrier is part of the one. 7. The method of claim 1 , wherein providing the die carrier comprises providing a substrate, wherein the substrate comprises the die carrier and is one out of a group consisting of a leadframe, a direct copper bonded substrate, a direct aluminum bonded substrate, and an active metal brazing substrate. 8. The method of claim 7 , wherein the substrate comprises a ceramic layer, in particular one or more of AlO, AlN, Al 2 O 3 , or a dielectric layer, in particular Si 3 N 4 . 9. The method of claim 1 , wherein the electrical connector is one out of a group consisting of a sleeve comprising an inner cavity, a metal block, and a metal layer of one of a direct copper bonded substrate, a direct aluminum bonded substrate, or an active metal brazing substrate. 10. The method of claim 1 , wherein an outer end of the metallic drilling screw extends through a first upper main face of the encapsulant opposite from the die carrier. 11. The method of claim 1 , further comprising: disposing a plurality of semiconductor dies on the die carrier, wherein at least one of the plurality of semiconductor dies comprises at least one contact pad on a main face remote from the die carrier; disposing a plurality of semiconductor diode dies on the die carrier, wherein at least one of the plurality of semiconductor diode dies is connected in parallel with at least one of the plurality of semiconductor dies; electrically connecting at least one of a plurality of electrical connectors with one of the contact pads of the semiconductor dies; and screwing at least one of a plurality of metallic drilling screws through the encapsulant and connecting the at least one of a plurality of metallic drilling screws with the electrical connector. 12. The method of claim 11 , further comprising: interconnecting the semiconductor dies and the semiconductor diode dies to form an AC/AC converter circuit, an AC/DC converter circuit, a DC/AC converter circuit, a frequency converter or a DC/DC converter circuit. 13. The method of to claim 1 , wherein the encapsulant comprises a first upper main face remote from the die carrier, and screwing the drilling screw is performed such that the drilling screw extends through the first main face of the encapsulant.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by arrangements for sealing or adhesion · CPC title

  • Package configurations · CPC title

  • by a substrate and the encapsulations · CPC title

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Frequently asked questions

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What does patent US12394697B2 cover?
A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semicondu…
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 19 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).