Display device having a gate disposed above an active area and a pattern disposed under the active area

Patent metadata

Field	Value
Publication number	US-12389773-B2
Application number	US-202418607630-A
Country	US
Kind code	B2
Filing date	Mar 18, 2024
Priority date	May 17, 2019
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A display device including: a panel including pixels, a pixel including: an LED; a capacitor between a first voltage line and a node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between a data line and a source of the first transistor; a third transistor between the node and a drain of the first transistor; a fourth transistor between the node and a second voltage line; a fifth transistor between the first voltage line and the source of the first transistor; a sixth transistor between the first electrode and the drain of the first transistor; and a seventh transistor between the second voltage line and the first electrode, the third and fourth transistor including: an active area including metal oxide; first and second gates above the active area; and a pattern below the active area.

First claim

What is claimed is:

1. A display device, comprising:
a display panel comprising a pixel, the pixel comprising:
a light emitting diode;
a capacitor connected between a first voltage line and a reference node;
a first transistor connected between the first voltage line and a first electrode of the light emitting diode;
a second transistor connected between a data line and a source of the first transistor;
a third transistor connected between the reference node and a drain of the first transistor;
a fourth transistor connected between the reference node and a second voltage line;
a fifth transistor connected between the first voltage line and the source of the first transistor;
a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor; and
a seventh transistor connected between the second voltage line and the first electrode of the light emitting diode, at least one of the third transistor and the fourth transistor comprising:
an active area comprising a metal oxide;
a source area extended from the active area;
a drain area extended from the active area;
a gate disposed above the active area; and
a pattern comprising a conductive material, disposed under the active area, and overlapping the active area when viewed in a plan view.

2. The display device of claim 1 , wherein the pattern comprises a metal.

3. The display device of claim 1 , wherein the active area of the fourth transistor extends from the active area of the third transistor.

4. The display device of claim 1 , wherein the first transistor comprises:
an active layer comprising polysilicon; and
a gate disposed above the active layer of the first transistor.

5. The display device of claim 4 , wherein the pattern and the gate of the first transistor are disposed on a same layer and comprise a same metal.

6. The display device of claim 4 , wherein the first transistor further comprises an upper electrode disposed on the gate of the first transistor, and
the pattern and the upper electrode are disposed on a same layer and comprise a same metal.

7. The display device of claim 1 , wherein the pattern and the second voltage line are disposed on a same layer and comprise a same metal.

8. The display device of claim 4 , wherein the at least one of the third transistor and the fourth transistor further comprises an additional pattern disposed below the pattern.

9. The display device of claim 1 , wherein each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is a N-type transistor.

10. The display device of claim 1 , wherein an active area of each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor comprises polysilicon.

11. A display device, comprising:
a display panel comprising a pixel, the pixel comprising:
a light emitting diode;
a capacitor connected between a first voltage line and a reference node;
a first transistor connected between the first voltage line and a first electrode of the light emitting diode;
a second transistor connected between a data line and a source of the first transistor;
a third transistor connected between the reference node and a drain of the first transistor;
a fourth transistor connected between the reference node and a second voltage line;
a fifth transistor connected between the first voltage line and the source of the first transistor;
a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor; and
a seventh transistor connected between the second voltage line and the first electrode of the light emitting diode, each of the third transistor and the fourth transistor comprising:
an active area comprising a metal oxide; and
a gate disposed above the active area, and
wherein the active area of the third transistor extends from the active area of the fourth transistor, and
each of the fifth transistor and the sixth transistor is one of a P-type transistor and a N-type transistor and each of the third transistor and the fourth transistor is the other one of the P-type transistor and the N-type transistor.

12. The display device of claim 11 , wherein at least one of the third transistor and the fourth transistor further comprises at least one pattern disposed under the active area, and overlapping the active area when viewed in a plan view.

13. The display device of claim 12 , wherein the at least one pattern comprises a first pattern comprising a metal.

14. The display device of claim 13 , wherein the at least one pattern further comprises a second pattern disposed under the first pattern and comprising polysilicon.

15. The display device of claim 12 , wherein the least one pattern comprises a conductive material or polysilicon.

16. The display device of claim 12 , wherein the least one pattern is disposed on a same layer as the second voltage line or a gate of the first transistor.

17. The display device of claim 11 , wherein each of the third transistor and the fourth transistor further comprises a pattern disposed under the active area, and overlapping the active area when viewed in a plan view, and
the pattern of the fourth transistor extends from the pattern of the third transistor.

18. The display device of claim 11 , wherein each of the third transistor and the fourth transistor further comprises a pattern disposed under the active area, and overlapping the active area when viewed in a plan view, and
the pattern of the third transistor extends from an active area of the first transistor.

19. The display device of claim 11 , wherein each of the fifth transistor and the sixth transistor comprises:
an active layer comprising polysilicon; and
a gate disposed on the active layer of the each of the fifth transistor and the sixth transistor.

20. The display device of claim 11 , wherein each of the first transistor and the second transistor is the one of the P-type transistor and the N-type transistor.

Assignees

• Samsung Display Co Ltd

Inventors

• Yun Suyeon
• Kim Sunghoon
• Ryu Anna

Classifications

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title