Integrated circuit device package

Patent metadata

Field	Value
Publication number	US-12389730-B2
Application number	US-202117495541-A
Country	US
Kind code	B2
Filing date	Oct 6, 2021
Priority date	Oct 6, 2020
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.

First claim

What is claimed is:

1. An apparatus comprising:
an integrated circuit having a first surface and terminals on the first surface;
a housing at least partially laterally surrounding the integrated circuit, the housing exposing the first surface; and
an electrical interconnect having a second surface and an opening, the second surface electrically coupled to the terminals on the first surface of the integrated circuit, the second surface contacting the housing, the opening exposing the first surface.

2. The apparatus of claim 1 , wherein the integrated circuit comprises an optical device.

3. The apparatus of claim 1 , wherein the integrated circuit includes a conductive film between the first surface of the integrated circuit and the second surface of the electrical interconnect.

4. The apparatus of claim 1 , wherein the integrated circuit includes a plurality of terminals on the first surface.

5. The apparatus of claim 1 , wherein the housing includes a third surface contacting the second surface of the electrical interconnect.

6. The apparatus of claim 1 , wherein the electrical interconnect includes the opening to expose an optical interface on the first surface of the integrated circuit.

7. The apparatus of claim 1 , wherein the electrical interconnect includes a first plurality of terminals and a second plurality of terminals on the second surface.

8. The apparatus of claim 1 , wherein the electrical interconnect includes a third surface, the opening configured to extend from the second surface to the third surface.

9. An apparatus comprising:
a first integrated circuit having a first surface;
a housing at least partially laterally surrounding the first integrated circuit, the housing having a second surface;
an electrical interconnect having a third surface, the third surface electrically coupled to the first surface, the third surface contacting the second surface; and
a second integrated circuit having a fourth surface, the fourth surface on the second surface, the fourth surface electrically coupled to the third surface.

10. The apparatus of claim 9 , wherein the first integrated circuit is an optical device.

11. The apparatus of claim 9 , wherein the first integrated circuit includes a plurality of terminals on the first surface.

12. The apparatus of claim 9 , wherein the housing includes a fifth surface contacting to the third surface.

13. The apparatus of claim 9 , wherein the electrical interconnect includes a first plurality of terminals and a second plurality of terminals on the third surface.

14. The apparatus of claim 9 , wherein the second integrated circuit includes a plurality of terminals on the fourth surface.

15. An apparatus comprising:
an integrated circuit including a first surface and a second surface;
a stand-off including a first surface and a second surface; and
an electrical interconnect having a first surface and a second surface, the first surface contacting first surface of the stand-off, the second surface contacting the second surface of the stand-off, the electrical interconnect electrically coupled to the second surface of the integrated circuit and to the first surface of the electrical interconnect.

16. The apparatus of claim 15 , wherein the integrated circuit is an optical device.

17. The apparatus of claim 15 , wherein the first surface of the integrated circuit is coupled to the first surface of the electrical interconnect through adhesive.

18. The apparatus of claim 15 , wherein the integrated circuit includes a plurality of terminals on the second surface of the integrated circuit.

19. The apparatus of claim 15 , wherein the electrical interconnect includes a plurality of terminals on a third surface.

20. The apparatus of claim 15 , wherein the electrical interconnect includes a fourth surface further including a plurality of terminals.

Assignees

• Texas Instruments Inc

Inventors

• Koduri Sreenivasan Kalyani
• Jacky Grimmett Dale

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• G02B6/4274 Primary

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title