Semiconductor structure and method of forming semiconductor structure

Patent metadata

Field	Value
Publication number	US-12389673-B2
Application number	US-202318397251-A
Country	US
Kind code	B2
Filing date	Dec 27, 2023
Priority date	Jul 24, 2020
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate including a first region and a second region;
a first isolation structure on the first region, and a first nanostructure and a second nanostructure on two sides of the first isolation structure respectively;
a second isolation structure on the second region, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure respectively, wherein a top of the second isolation structure is lower than a top of the first isolation structure;
a first gate structure and a second gate structure on the first region, wherein the first gate structure is on the first nanostructure, the second gate structure is on the second nanostructure, and the first gate structure and the second gate structure together expose a top surface of the first isolation structure; and
a third gate structure and a fourth gate structure on the second region, wherein the third gate structure is on the third nanostructure, the fourth gate structure is on the fourth nanostructure, and the third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

2. The semiconductor structure according to claim 1 , wherein:
the first isolation structure has a height in a range approximately from 10 nanometers to 100 nanometers.

3. The semiconductor structure according to claim 1 , wherein:
the second isolation structure is lower than the first isolation structure; and
a height difference between the second isolation structure and the first isolation structure is in a range approximately from 0 nanometer to 50 nanometers.

4. The semiconductor structure according to claim 1 , wherein:
the first isolation structure between the first nanostructure and the second nanostructure has a width in a range approximately from 2 nanometers to 50 nanometers; and
the second isolation structure between the third nanostructure and the fourth nanostructure has a width in a range approximately from 2 nanometers to 50 nanometers.

5. The semiconductor structure according to claim 1 , further comprising:
a first isolation layer on the first region, wherein the first isolation layer is on a portion of a sidewall of the first nanostructure and a portion of a sidewall of the second nanostructure, and a top surface of the first isolation layer is lower than a top surface of the first nanostructure and a top surface of the second nanostructure; and
a second isolation layer on the second region, wherein the second isolation layer is on a portion of a sidewall of the third nanostructure and a portion of a sidewall of the fourth nanostructure, and a top surface of the second isolation layer is lower than a top surface of the third nanostructure and a top surface of the fourth nanostructure.

6. The semiconductor structure according to claim 1 , wherein:
the first isolation structure is made of a material including a dielectric material, wherein the dielectric material includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, nitrogen silicon carbide, nitrogen silicon oxycarbide, or a combination thereof; and
the second isolation structure is made of a material including a dielectric material, wherein the dielectric material includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, nitrogen silicon carbide, nitrogen silicon oxycarbide, or a combination thereof.

7. The semiconductor structure according to claim 1 , further comprising a dielectric layer on the substrate, wherein:
the dielectric layer is on a sidewall of the first gate structure, a sidewall of the second gate structure, a sidewall of the third gate structure, and a sidewall of the fourth gate structure.

8. A method of forming a semiconductor structure, comprising:
providing a substrate, the substrate including a first region and a second region;
forming a first isolation structure on the first region, and a first nanostructure and a second nanostructure on two sides of the first isolation structure respectively;
forming a second isolation structure on the second region, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure respectively, wherein a top of the second isolation structure is lower than a top of the first isolation structure;
forming a first gate structure and a second gate structure on the first region, wherein the first gate structure is on the first nanostructure, the second gate structure is on the second nanostructure, and the first gate structure and the second gate structure together expose a top surface of the first isolation structure; and
forming a third gate structure and a fourth gate structure on the second region, wherein the third gate structure is on the third nanostructure, the fourth gate structure is on the fourth nanostructure, and the third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

9. The method according to claim 8 , wherein a process of forming the first isolation structure and the second isolation structure includes:
forming a stacked material structure on the substrate, wherein the stacked material structure includes a stack of a plurality of nanowire material layers and a sacrificial material layer on a nanowire material layer of the plurality of nanowire material layers;
forming a first opening in the stacked material structure on the first region, and forming a second opening in the stacked material structure on the second region;
forming a first isolation structure in the first opening, and forming an initial isolation structure in the second opening; and
removing a portion of the initial isolation structure on the second region, and forming a second isolation structure on the second region.

10. The method according to claim 9 , wherein a process of removing the portion of the initial isolation structure on the second region includes:
forming a first mask layer on the substrate, wherein the first mask layer exposes a surface of the second region; and
using the first mask layer as a mask, etching the initial isolation structure on the second region, thereby forming the second isolation structure.

11. The method according to claim 10 , wherein:
a process of etching the initial isolation structure on the second region includes a dry etching process.

12. The method according to claim 9 , wherein a process of forming the first opening and the second opening includes:
forming a second mask layer on the stacked material structure, wherein the second mask layer exposes a portion of a surface of the sacrificial material layer;
using the second mask layer as a mask, removing a portion of the stacked material structure until a surface of the substrate is exposed, forming a first opening in the stacked material structure on the first region, and forming an initial first nanostructure and an initial second nanostructure on the first region, wherein the initial first nanostructure includes a plurality of first composite layers, a first composite layer of the plurality of first composite layers includes a first nanowire and a first sacrificial layer on the first nanowire, the initial second nanostructure includes a plurality of second composite layers, and a second composite layer of the plurality of second composite layers includes a second nanowire and a second sacrificial layer on the second nanowire; and
forming a second opening in the stacked material structure on the second regi

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Chen Jian
• Ji Shiliang
• Zhang Haiyang

Classifications

• H10D84/0179

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D84/833

  comprising forksheet IGFETs · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title