Semiconductor device and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12389596-B2
Application number	US-202117467568-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Nov 13, 2020
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first structure including a peripheral circuit; and
a second structure disposed on the first structure and bonded to the first structure,
wherein the second structure includes:
a pattern structure including a polysilicon layer;
an upper insulating layer disposed on the pattern structure;
a stack structure disposed between the first structure and the pattern structure and including a first stack portion and a second stack portion spaced apart from each other in a horizontal direction, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked in a vertical direction;
separation structures penetrating through the stack structure and separating the stack structure;
memory vertical structures penetrating through the first stack portion of the stack structure;
bit lines below the memory vertical structures and electrically connected to the memory vertical structures, and
a contact structure penetrating through the second stack portion of the stack structure, the pattern structure, and the upper insulating layer,

wherein the contact structure includes:
a lower contact plug penetrating through at least the second stack portion of the stack structure and spaced apart from the horizontal conductive layers of the second stack portion; and
an upper contact plug in contact with the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer,

wherein the polysilicon layer of the pattern structure is spaced apart from the lower contact plug and the upper contact plug and is in contact with the separation structures, and
wherein the bit lines are not electrically connected to the contact structure and the separation structures.

2. The semiconductor device of claim 1 , wherein the upper contact plug is in contact with an upper surface of the lower contact plug and a side surface of the lower contact plug, adjacent to the upper surface thereof.

3. The semiconductor device of claim 2 ,
wherein the lower contact plug further includes a portion extending into the pattern structure from a portion penetrating through the second stack portion of the stack structure, and
wherein the upper surface of the lower contact plug is disposed at a height level between a lower surface of the pattern structure and an upper surface of the pattern structure.

4. The semiconductor device of claim 3 , wherein a height difference between the upper surface of the lower contact plug and the lower surface of the pattern structure is smaller than a height difference between the upper surface of the lower contact plug and the upper surface of the pattern structure.

5. The semiconductor device of claim 1 ,
wherein the contact structure further includes an insulating lower spacer covering a side surface of the lower contact plug, and an insulating upper spacer covering a side surface of the upper contact plug, and
wherein a thickness of the insulating upper spacer in the horizontal direction is greater than a thickness of the insulating lower spacer in the horizontal direction.

6. The semiconductor device of claim 1 ,
wherein the contact structure further includes an insulating lower spacer covering a side surface of the lower contact plug,
wherein each of the separation structures includes a conductive separation pattern and an insulating separation spacer covering a side surface of the conductive separation pattern,
wherein the lower contact plug includes a first liner layer and a first pillar pattern,
wherein the conductive separation pattern includes a second liner layer formed of the same material as the first liner layer and a second pillar pattern formed of the same material as the first pillar pattern,
wherein the first liner layer covers at least a side surface of the first pillar pattern, and
wherein the second liner layer covers a side surface of the second pillar pattern and an upper surface of the second pillar pattern.

7. The semiconductor device of claim 6 ,
wherein the first liner layer includes a portion interposed between the first pillar pattern and the upper contact plug, and
wherein the first pillar pattern is spaced apart from the upper contact plug.

8. The semiconductor device of claim 6 , wherein the first pillar pattern is in contact with the upper contact plug.

9. The semiconductor device of claim 1 ,
wherein the first structure includes first bonding pads, and
wherein the second structure further includes:
gate contact plugs disposed under the stack structure and electrically connected to word lines and selection gate electrodes of the horizontal conductive layers of the first stack portion;
bit lines disposed between the memory vertical structures and the first structure, and electrically connected to the memory vertical structures;
gate interconnections disposed between the gate contact plugs and the first structure, and electrically connected to the gate contact plugs;
a contact interconnection disposed between the contact structure and the first structure, and electrically connected to the lower contact plug;
second bonding pads in contact with and bonded to the first bonding pads; and
an interconnection structure electrically connecting the second bonding pads with the bit lines, the gate interconnections, and the contact interconnection.

10. The semiconductor device of claim 9 ,
wherein the first stack portion includes a first stacked region and a second stacked region disposed on the first stacked region,
wherein the first stacked region includes a plurality of first horizontal conductive layers of the horizontal conductive layers,
wherein the second stacked region includes a plurality of second horizontal conductive layers of the horizontal conductive layers, and
wherein a side surface of at least one of the memory vertical structures has a bent portion between the plurality of first horizontal conductive layers and the plurality of second horizontal conductive layers.

11. The semiconductor device of claim 1 , wherein one of the separation structures is disposed between the first stack portion and the second stack portion.

12. The semiconductor device of claim 1 ,
wherein the second structure further includes a capping insulating layer,
wherein the stack structure includes a first stack structure including the first stack portion and a dummy stack structure including the second stack portion,
wherein the memory vertical structures do not penetrate through the dummy stack structure, and
wherein at least a portion of the capping insulating layer is disposed between the first stack structure and the dummy stack structure.

13. The semiconductor device of claim 1 ,
wherein the pattern structure has a lower surface facing the first structure and an upper surface opposing the lower surface,
wherein each of the separation structures includes a conductive separation pattern and an insulating separation spacer covering a side surface of the conductive separation pattern,
wherein the conductive separation pattern of at least one of the separation structures further includes a portion extending into the pattern structure from a portion penetrating through the stack structure,
wherein the conductive separation pattern has an upper surface disposed at a height level between an upper surface of the pattern structure and a lower surface of the pattern structure, and
wherein a height difference between the upper surface of the conductive separation pattern and the lower surface of the pattern structure is greater than

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jaeho
• Kim Jiwon
• Hwang Sungmin
• Lim Joonsung
• Sung Sukkang

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title