Timer-based resolver integral demodulation

Patent metadata

Field	Value
Publication number	US-12388461-B2
Application number	US-202318348435-A
Country	US
Kind code	B2
Filing date	Jul 7, 2023
Priority date	Mar 16, 2023
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A digital signal processing system to determine a position of a resolver includes a digital signal processor that includes first timer and second timer. The first timer creates a resolver excitation signal from a series of samples and creates an incrementing Crossing signal each time the resolver excitation signal crosses zero. When the Crossing signal has a first value, a multiplexer provides resolver sine signals to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in a sine sample buffer. When the Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer stores the series of digital cosine samples in a buffer.

First claim

What is claimed is:

1. A method for determining a location of a resolver, the method comprising:
creating a resolver excitation signal from a series of samples;
generating an incrementing Select/Zero Crossing signal that increments each time the resolver excitation signal crosses zero;
providing the resolver excitation signal to the resolver;
receiving at a multiplexer resolver sine and resolver cosine signals from the resolver that are based on the excitation signal;
when the Select/Zero Crossing signal has a first value, providing the resolver sine signal to an analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and storing the series of digital sine samples in a sine sample buffer;
when the Select/Zero Crossing signal has a second value, providing the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and storing the series of digital cosine samples in a cosine sample buffer;
determining a sine amplitude-based series of digital sine samples;
determining a cosine amplitude-based series of digital cosine samples; and
identifying a quadrant of the resolver position based on the sine and cosine amplitudes.

2. The method of claim 1 , wherein the resolver sine samples and the resolver cosine samples are collected at different times.

3. The method of claim 2 , wherein the resolver sine samples and the resolver cosine samples are each created for a half period of the resolver excitation signal.

4. The method of claim 1 , wherein identifying the quadrant of the resolver position comprises doubling the sine amplitude and the cosine amplitude.

5. The method of claim 1 , wherein the resolver excitation signal is created by a first timer.

6. The method of claim 5 , wherein the first timer is a N2HET timer.

7. The method of claim 1 , further comprising:
providing the digital sine samples to a second timer, wherein the second timer provides the digital sine samples to the sine sample buffer based on the Select/Zero Crossing signal.

8. The method of claim 7 , further comprising:
providing the digital cosine samples to the second timer, wherein the second timer provides the digital cosine samples to the cosine sample buffer based on the Select/Zero Crossing signal.

9. The method of claim 8 , wherein the second timer is a N2HET timer.

10. The method of claim 5 , wherein the first timer creates the Select/Zero Crossing signal and provides it to the multiplier and to a second timer.

11. A digital signal processing system to determine a position of a resolver, the system comprising:
a digital signal processor that includes first timer and second timer, wherein the first timer creates a resolver excitation signal from a series of samples and creates an incrementing Select/Zero Crossing signal each the resolver excitation signal crosses zero;
a multiplexer configured to receive resolver sine and resolver cosine signals from the resolver that are based on the excitation signal, the multiplexer having a select input receiving the Select/Zero Crossing signal;
an analog to digital converter connected to an output of the multiplexer, the analog to digital converter having an output connected to the second timer; and
a memory buffer connected to the second timer that includes a sine sample buffer and a cosine sample buffer;
wherein when the Select/Zero Crossing signal has a first value, the multiplexer provides the resolver sine signal to the analog to digital converter to convert the resolver sine signal to a series of digital sine samples, and the second timer stores the series of digital sine samples in the sine sample buffer; and
wherein when the Select/Zero Crossing signal has a second value, the multiplexer provides the resolver cosine signal to the analog to digital converter to convert the resolver cosine signal to a series of digital cosine samples, and the second timer storing the series of digital cosine samples in the cosine sample buffer.

12. The system of claim 11 , wherein the resolver sine samples and the resolver cosine samples are collected at different times.

13. The system of claim 12 , wherein the resolver sine samples and the resolver cosine samples are each created for a half period of the resolver excitation signal.

14. The system of claim 11 , wherein the first timer is a N2HET timer.

15. The method of claim 14 , wherein the second timer is a N2HET timer and the first timer provides the Select/Zero Crossing signal to the second timer.

Assignees

• Hamilton Sundstrand Corp

Inventors

• Nagaraju Divya
• Vijay Ashish
• Kaliyugavaratharajan Sundaram
• Thiagarajan Kannan

Classifications

• H03M1/485

  for position encoding, e.g. using resolvers or synchros · CPC title

• G01D5/2073

  by movement of a single coil with respect to two or more coils · CPC title

• H03M1/645 Primary

  for position encoding, e.g. using resolvers or synchros (H03M1/485 takes precedence) · CPC title

• G01D5/204 Primary

  by influencing the mutual induction between two or more coils (G01D5/22 takes precedence) · CPC title